EM351-RTR datasheet(117/241 Pages) SILABS

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117

Rev 1.3

and External Trigger Synchronization" on page 136 to get more details on counter enabling.

Note that the actual counter enable signal CNT_EN is set one clock cycle after TIM_CEN.

Note:

When the EM35x enters debug mode and the ARM® CortexTM-M3 core is halted, the counters continue to run normally.

9.3.1.1. Prescaler

The prescaler can divide the counter clock frequency by power of two from 1 through 32768. It is based on a 16-bit

counter controlled through the 4-bit TIM_PSCEXP bit field in the TIMx_PSC register. The factor by which the

counter is divided is two raised to the power TIM_PSCEXP (2TIM_PSCEXP).

It can be changed on the fly as this control register is buffered. The new prescaler ratio is used starting at the next

UEV.

Figure 9.2 gives an example of the counter behavior when the prescaler ratio is changed on the fly.

Figure 9.2. Counter Modes

9.3.2. Counter Modes

9.3.2.1. Up-Counting Mode

In up-counting mode, the counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then

restarts from 0 and generates a counter overflow event.

A UEV can be generated at each counter overflow, by setting the TIM_UG bit in the TIMx_EGR register, or by

using the slave mode controller.

Software can disable the UEV by setting the TIM_UDIS bit in the TIMx_CR1 register, to avoid updating the shadow

registers while writing new values in the buffer registers. No UEV will occur until the TIM_UDIS bit is written to 0.

Both the counter and the prescaler counter restart from 0, but the prescale rate does not change. In addition, if the

TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit generates a UEV but without setting the

INT_TIMUIF flag. Thus no interrupt request is sent. This avoids generating both update and capture interrupts

when clearing the counter on the capture event.

When a UEV occurs, the update flag (the INT_TIMUIF bit in the INT_TIMxFLAG register) is set (unless TIM_URS

is 1) and the following registers are updated:



The buffer of the prescaler is reloaded with the buffer value (contents of the TIMx_PSC register).



The auto-reload shadow register is updated with the buffer value (TIMx_ARR).



Figures 9.3, 9.4, 9.5, and 9.6 show some examples of the counter behavior for different clock frequencies when

TIMx_ARR = 0x36.

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