AIS2120SX datasheet(42/58 Pages) STMICROELECTRONICS

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Interface description

AIS1120SX / AIS2120SX

42/58

DocID028312 Rev 3

Interface description

The AIS1120SX / AIS2120SX provides a bi-directional 3.3 V SPI interface for

communication with the MCU at a 32-bit data word size. Each transfer consists of two

frames of 32 clocks per frame.

The sensor always operates in slave mode whereas the MCU provides the master function.

The interface consists of 4 ports as shown below.

Figure 22. SPI

Serial clock (SCK): input for master clock signal. This clock determines the speed of data

transfer and all receiving and sending is done synchronous to this clock.

Chip Select (CS): CS activates the SPI interface. As long as CS is high, the IC does not

accept the clock signal or data and the output SDO is in high impedance. Whenever CS is in

a low logic state, data can be transferred from and to the microcontroller.

Serial Input (SDI): accelerometer data in is latched by the rising edge of SCL (see

Figure 23: SPI timings).

Serial Output (SDO): accelerometer data out is set by the falling edge of SCL (see

Figure 23: SPI timings).

5.1

32-bit communication protocol

The communication between slave and master is transmitted by 32-bit data word, MSB first.

An off-frame protocol is used meaning that each transfer is completed through a sequence

of 2 phases.

The answer of a given request is sent within the very next frame.

The acceleration data for the x-axis, y-axis channel will be frozen at the rising edge of CS of

the Request and submitted during the Response (see Figure 23).

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