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AIS2120SX bảng dữ liệu(PDF) 33 Page - STMicroelectronics

tên linh kiện AIS2120SX
Giải thích chi tiết về linh kiện  Embedded self-test
PDF  58 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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AIS2120SX bảng dữ liệu(HTML) 33 Page - STMicroelectronics

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AIS1120SX / AIS2120SX
Power-on phase and initialization
58
3.3
Phase2 (T2): configuration
Once nPOR is asserted, the device will initialize the registers to the default settings and
start ASIC diagnostic procedure. If an error is detected, the corresponding error bit will be
set in DEVSTAT register. This phase is characterized by (ST1:ST0 = "00").
Figure 19. Phase 2 state flow
The diagnostic procedure in this stage includes cap-loss detection, charge pump check for
self-test, and VREG/VCC low-voltage monitoring. Cap-loss mode is initiated after EEPROM
download where the regulator is disabled 1 μs. Without a load cap the regulator voltage
would fall below the UV threshold and the device latches it as cap-loss flag.
Figure 20. Cap-loss detection



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