AT89C51CC03U-RDTIM datasheet(138/195 Pages) ATMEL

138 / 195 page

138

AT89C51CC03

4182I–CAN–06/05

Figure 66. SPI Interrupt Requests Generation

Registers

Three registers in the SPI module provide control, status and data storage functions.

These registers are describe in the following paragraphs.

Serial Peripheral Control

•

The Serial Peripheral Control Register does the following:

•

Selects one of the Master clock rates

•

Configure the SPI Module as Master or Slave

•

Selects serial clock polarity and phase

•

Enables the SPI Module

•

Frees the SS pin for a general-purpose

Table 92 describes this register and explains the use of each bit

Table 92. SPCON Register

SPCON - Serial Peripheral Control Register (0D4H)

SPI

CPU Interrupt Request

SPIF

SPTEIE

SPTE

MODF

MODFIE

543

210

SPR2

SPEN

SSDIS

MSTR

CPOL

CPHA

SPR1

SPR0

Bit Number

Bit Mnemonic

Description

SPR2

Serial Peripheral Rate 2

Bit with SPR1 and SPR0 define the clock rate (See bits SPR1 and

SPR0 for detail).

SPEN

Serial Peripheral Enable

Cleared to disable the SPI interface (internal reset of the SPI).

Set to enable the SPI interface.

SSDIS

SS Disable

Cleared to enable SS in both Master and Slave modes.

Set to disable SS in both Master and Slave modes. In Slave mode,

this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF

interrupt request is generated

4MSTR

Serial Peripheral Master

Cleared to configure the SPI as a Slave.

Set to configure the SPI as a Master.

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