AT89C51CC03U-RDTIM datasheet(71/195 Pages) ATMEL

71 / 195 page

AT89C51CC03

4182I–CAN–06/05

Mode 2 (8-bit Timer with Auto-

Reload)

Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads

from TH0 register (see Figure 37). TL0 overflow sets TF0 flag in TCON register and

reloads TL0 with the contents of TH0, which is preset by software. When the interrupt

request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next

reload value may be changed at any time by writing it to TH0 register.

Figure 37. Timer/Counter x (x = 0 or 1) in Mode 2

Mode 3 (Two 8-bit Timers)

Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit

Timers (see Figure 38). This mode is provided for applications requiring an additional 8-

bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg-

ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a

Timer function (counting FPER /6) and takes over use of the Timer 1 interrupt (TF1) and

run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode

Figure 38. Timer/Counter 0 in Mode 3: Two 8-bit Counters

TRx

TCON reg

TFx

TCON reg

GATEx

TMOD reg

Overflow

Timer x

Interrupt

Request

C/Tx#

TMOD reg

TLx

(8 bits)

THx

(8 bits)

INTx#

FTx

CLOCK

÷ 6

See the “Clock” section

TR0

TCON.4

TF0

TCON.5

INT0#

GATE0

TMOD.3

Overflow

Timer 0

Interrupt

Request

C/T0#

TMOD.2

TL0

(8 bits)

TR1

TCON.6

TH0

(8 bits)

TF1

TCON.7

Overflow

Timer 1

Interrupt

Request

FTx

CLOCK

÷ 6

FTx

CLOCK

÷ 6

See the “Clock” section

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