AT89C51CC03U-RDTIM datasheet(136/195 Pages) ATMEL

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136

AT89C51CC03

4182I–CAN–06/05

Error Conditions

The following flags in the SPSCR register indicate the SPI error conditions:

Mode Fault Error (MODF)

Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS)

pin is inconsistent with the actual mode of the device.

•

Mode fault detection in Master mode:

MODF is set to warn that there may be a multi-master conflict for system control. In this

case, the SPI system is affected in the following ways:

–

An SPI receiver/error CPU interrupt request is generated

–

The SPEN bit in SPCON is cleared. This disables the SPI

–

The MSTR bit in SPCON is cleared

Clearing the MODF bit is accomplished by a read of SPSCR register with MODF bit set,

followed by a write to the SPCON register. SPEN Control bit may be restored to its orig-

inal set state after the MODF bit has been cleared.

Figure 64. Mode Fault Conditions in Master Mode (Cpha =’1’/Cpol =’0’)

Note:

When SS is discarded (SS disabled) it is not possible to detect a MODF error in master

mode because the SPI is internally unselected and the SS pin is a general purpose I/O.

•

Mode fault detection in Slave mode

In slave mode, the MODF error is detected when SS goes high during a transmission.

A transmission begins when SS goes low and ends once the incoming SCK goes back

to its idle level following the shift of the eighteen data bit.

A MODF error occurs if a slave is selected (SS is low) and later unselected (SS is high)

even if no SCK is sent to that slave.

At any time, a ’1’ on the SS pin of a slave SPI puts the MISO pin in a high impedance

state and internal state counter is cleared. Also, the slave SPI ignores all incoming SCK

clocks, even if it was already in the middle of a transmission. A new transmission will be

performed as soon as SS pin returns low.

SCK

(master)

SCK cycle #

(slave)

(from master)

MODF detected

MSB

SPI enable

MODF detected

MOSI

MISO

(from master)

(from slave)

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