AD7477AARM datasheet(16/24 Pages) AD

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REV. C

–16–

AD7476A/AD7477A/AD7478A

Table II provides some typical performance data with various

op amps used as the input buffer for a 100 kHz input tone at

room temperature under the same setup conditions.

Table II. AD7476A Typical Performance with Various

Input Buffers, VDD = 3 V

Op Amp in the

AD7476A SNR Performance

Input Buffer

(dB)

AD711

72.3

AD797

72.5

AD845

71.4

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance will depend on the amount of total harmonic

distortion (THD) that can be tolerated. The THD will increase

as the source impedance increases and the performance will

degrade. See TPC 7.

Digital Inputs

The digital inputs applied to the AD7476A/AD7477A/AD7478A

are not limited by the maximum ratings that limit the analog

input. Instead, the digital inputs applied can go to 7 V and are

not restricted by the VDD + 0.3 V limit as on the analog input.

For example, if the AD7476A/AD7477A/AD7478A were oper-

ated with a VDD of 3 V, then 5 V logic levels could be used on

the digital inputs. However, it is important to note that the data

output on SDATA will still have 3 V logic levels when VDD = 3 V.

Another advantage of SCLK and

CS not being restricted by the

VDD + 0.3 V limit is the fact that power supply sequencing

issues are avoided. If

CS or SCLK is applied before V

DD, there

is no risk of latch-up as there would be on the analog input if a

signal greater than 0.3 V was applied prior to VDD.

MODES OF OPERATION

The mode of operation of the AD7476A/AD7477A/AD7478A is

selected by controlling the (logic) state of the

CS signal during a

conversion. There are two possible modes of operation: normal

and power-down. The point at which

CS is pulled high after the

conversion has been initiated will determine whether the

AD7476A/AD7477A/AD7478A will enter power-down mode or

not. Similarly, if already in power-down,

CS can control

whether the device will return to normal operation or remain in

power-down. These modes of operation are designed to provide

flexible power management options. These options can be

chosen to optimize the power dissipation/throughput rate ratio for

different application requirements.

Normal Mode

This mode is intended for the fastest throughput rate perfor-

mance; the user does not have to worry about any power-up

times with the AD7476A/AD7477A/AD7478A remaining fully

powered all the time. Figure 9 shows the general diagram of the

operation of the AD7476A/AD7477A/AD7478A in this mode.

The conversion is initiated on the falling edge of

CS as described

in the Serial Interface section. To ensure that the part remains

fully powered up at all times,

CS must remain low until at least

10 SCLK falling edges have elapsed after the falling edge of

CS.

CS is brought high any time after the 10th SCLK falling edge

but before the end of the tCONVERT, the part will remain pow-

ered up, but the conversion will be terminated and SDATA will

go back into three-state.

For the AD7476A, 16 serial clock cycles are required to com-

plete the conversion and access the complete conversion results.

For the AD7477A and AD7478A, a minimum of 14 and 12

serial clock cycles are required to complete the conversion and

access the complete conversion results, respectively.

CS may idle high until the next conversion or may idle low until

CS returns high sometime prior to the next conversion (effec-

tively idling

CS low).

Once a data transfer is complete (SDATA has returned to

three-state), another conversion can be initiated after the quiet

time, tQUIET, has elapsed by bringing CS low again.

Power-Down Mode

This mode is intended for use in applications where slower

throughput rates are required; either the ADC is powered down

between each conversion, or a series of conversions is performed

at a high throughput rate and the ADC is then powered down

for a relatively long duration between these bursts of several

conversions. When the AD7476A/AD7477A/AD7478A is in

power-down, all analog circuitry is powered down.

To enter power-down, the conversion process must be inter-

rupted by bringing

CS high anywhere after the second falling

edge of SCLK and before the 10th falling edge of SCLK, as

shown in Figure 10. Once

CS has been brought high in this

window of SCLKs, the part will enter power-down, the con-

version that was initiated by the falling edge of

CS will be

terminated, and SDATA will go back into three-state. If

CS is

brought high before the second SCLK falling edge, the part will

remain in normal mode and will not power down. This will

avoid accidental power-down due to glitches on the

CS line.

In order to exit this mode of operation and power up the

AD7476A/AD7477A/AD7478A again, a dummy conversion is

performed. On the falling edge of

CS, the device will begin to

power up and will continue to power up as long as

CS is held low

until after the falling edge of the 10th SCLK. The device will be

fully powered up once 16 SCLKs have elapsed, and valid data

will result from the next conversion as shown in Figure 11. If

is brought high before the 10th falling edge of SCLK, then the

AD7476A/AD7477A/AD7478A will go back into power-down.

This avoids accidental power-up due to glitches on the

CS line or

an inadvertent burst of eight SCLK cycles while

CS is low. So

although the device may begin to power up on the falling edge of

CS, it will power down again on the rising edge of CS as long as it

occurs before the 10th SCLK falling edge.

Power-Up Time

The power-up time of the AD7476A/AD7477A/AD7478A is

µs, which means that with any frequency of SCLK up to 20 MHz,

one dummy cycle will always be sufficient to allow the device to

power up. Once the dummy cycle is complete, the ADC will be

fully powered up and the input signal will be acquired properly.

The quiet time, tQUIET, must still be allowed from the point

where the bus goes back into three-state after the dummy con-

version to the next falling edge of

CS. When running at a 1 MSPS

throughput rate, the AD7476A/AD7477A/AD7478A will power

up and acquire a signal within

± 0.5 LSB in one dummy

cycle, i.e., 1

µs.

When powering up from the power-down mode with a dummy

cycle, as in Figure 11, the track-and-hold that was in hold mode

while the part was powered down returns to track mode after

the first SCLK edge the part receives after the falling edge of

CS. This is shown as Point A in Figure 11. Although at any

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