AD7477AARM datasheet(14/24 Pages) AD

14 / 24 page

REV. C

–14–

AD7476A/AD7477A/AD7478A

CIRCUIT INFORMATION

The AD7476A/AD7477A/AD7478A are fast, micropower,

12-/10-/8-bit, single-supply A/D converters, respectively. The

parts can be operated from a 2.35 V to 5.25 V supply. When

operated from either a 5 V supply or a 3 V supply, the AD7476A/

AD7477A/AD7478A are capable of throughput rates of 1 MSPS

when provided with a 20 MHz clock.

The AD7476A/AD7477A/AD7478A provide the user with an

on-chip, track-and-hold A/D converter and a serial interface

housed in a tiny 6-lead SC70 or 8-lead MSOP package, which

offer the user considerable space-saving advantages over alterna-

tive solutions. The serial clock input accesses data from the part

but also provides the clock source for the successive-approximation

A/D converter. The analog input range is 0 V to VDD. The ADC

does not require an external reference or an on-chip reference.

The reference for the AD7476A/AD7477A/AD7478A is derived

from the power supply and thus gives the widest dynamic input

range.

The AD7476A/AD7477A/AD7478A also feature a power-down

option to allow power saving between conversions. The power-

down feature is implemented across the standard serial interface,

as described in the Modes of Operation section.

CONVERTER OPERATION

The AD7476A/AD7477A/AD7478A is a successive-approximation,

analog-to-digital converter based around a charge redistribution

DAC. Figures 4 and 5 show simplified schematics of the ADC.

Figure 4 shows the ADC during its acquisition phase. SW2 is

closed and SW1 is in Position A, the comparator is held in a

balanced condition, and the sampling capacitor acquires the

signal on VIN.

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

COMPARATOR

SW2

SAMPLING

CAPACITOR

ACQUISITION

PHASE

SW1

AGND

VDD/2

VIN

Figure 4. ADC Acquisition Phase

When the ADC starts a conversion, see Figure 5, SW2 will open and

SW1 will move to Position B, causing the comparator to become

unbalanced. The control logic and the charge redistribution

DAC are used to add and subtract fixed amounts of charge from

the sampling capacitor to bring the comparator back into a

balanced condition. When the comparator is rebalanced, the

conversion is complete. The control logic generates the ADC

output code. Figure 6 shows the ADC transfer function.

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

COMPARATOR

SW2

SAMPLING

CAPACITOR

CONVERSION

PHASE

SW1

AGND

VDD/2

VIN

Figure 5. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding of the AD7476A/AD7477A/AD7478A is

straight binary.

The designed code transitions occur at the successive integer

LSB values, i.e., 1 LSB, 2 LSB, and so on. The LSB size is

VDD/4096 for the AD7476A, VDD/1024 for the AD7477A, and

VDD/256 for the AD7478A. The ideal transfer characteristic for

the AD7476A/AD7477A/AD7478A is shown in Figure 6.

000...000

ANALOG INPUT

111...111

000...001

000...010

111...110

111...000

011...111

1LSB = VDD/256 (AD7478A)

1LSB

+VDD – 1LSB

1LSB = VDD/1024 (AD7477A)

1LSB = VDD/4096 (AD7476A)

Figure 6. AD7476A/AD7477A/AD7478A

Transfer Characteristic

AD7477AARM bảng dữ liệu(PDF) 14 Page - Analog Devices

AD7477AARM bảng dữ liệu(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

bảng dữ liệu tải về

Link URL