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LM98501CCVBH bảng dữ liệu(PDF) 17 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện LM98501CCVBH
Giải thích chi tiết về linh kiện  10-Bit, 27 MSPS Camera Signal Processor
PDF  24 Pages
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Trang chủ  http://www.national.com
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LM98501CCVBH bảng dữ liệu(HTML) 17 Page - National Semiconductor (TI)

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Register Memory Map
Register Data
The following section describes all available registers in the
LM98501 register bank and their functions.
PGA GAIN REGISTERS
Register Name PGA Gain 0
Address
0 Hex
Type
Read/Write
Reset Value
0000 0000 Binary
Bit
Bit Symbol
Description
[7:0]
PGA Gain
0.0 dB–32.0 dB in 0.125 dB
steps.
Register Name PGA Gain 1
Address
1 Hex
Type
Read/Write
Reset Value
0000 0000 Binary
Bit
Bit Symbol
Description
[7:0]
PGA Gain
0.0 dB–32.0 dB in 0.125 dB
steps.
Register Name PGA Gain 2
Address
2 Hex
Type
Read/Write
Reset Value
0000 0000 Binary
Bit
Bit Symbol
Description
[7:0]
PGA Gain
0.0 dB–32.0 dB in 0.125 dB
steps.
Register Name PGA Gain 3
Address
3 Hex
Type
Read/Write
Reset Value
0000 0000 Binary
Bit
Bit Symbol
Description
[7:0]
PGA Gain
0.0 dB–32.0 dB in 0.125 dB
steps.
ANALOG OFFSET REGISTERS
Register Name Analog Offset 0
Address
4 Hex
Type
Read/Write
Reset Value
0000 0000 Binary
Bit
Bit Symbol
Description
[7:0]
Signed Analog
Offset
Digital representation of the
analog offset to be applied to
the input of the PGA. See
“Analog Offset” on page 15.
Register Name Analog Offset 1
Address
5 Hex
Type
Read/Write
Reset Value
0000 0000 Binary
Bit
Bit Symbol
Description
[7:0]
Signed Analog
Offset
Digital representation of the
analog offset to be applied to
the input of the PGA. See
“Analog Offset” on page 15.
Register Name Analog Offset 2
Address
6 Hex
Type
Read/Write
Reset Value
0000 0000 Binary
Title
Address
Default Value
PGA Gain 0
0000
0000 0000 (0d)
PGA Gain 1
0001
0000 0000 (0d)
PGA Gain 2
0010
0000 0000 (0d)
PGA Gain 3
0011
0000 0000 (0d)
Analog Offset 0
0100
0000 0000 (0d)
Analog Offset 1
0101
0000 0000 (0d)
Analog Offset 2
0110
0000 0000 (0d)
Analog Offset 3
0111
0000 0000 (0d)
CFA Configuration 0
1000
0000 0000 (0d)
CFA Configuration 1
1001
0000 0000 (0d)
CFA Definition
1010
XXXX 0000 (0d)
Output Black Level
1011
0001 0000 (32d)
Software Control 0
1100
0100 1110 (78d)
Software Control 1
1101
XX00 0X00 (0d)
Power Level Control 0
1110
1010 1010 (170d)
Power Level Control 1
1111
0101 1010 (90d)
FIGURE 12. Register Memory Map
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