LM98501CCVBH datasheet(13/24 Pages) NSC

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Digital Output Timing

System Timing

System Overview

INTRODUCTION

The LM98501 is a 10-bit, complete analog-to-digital camera

signal processor for use with CCD imager systems operating

from a single +3V supply. The internal processing is carefully

optimized to maintain the signal-to-noise ratio and excellent

dynamic performance of most popular CCD imagers. The

system block diagram of the LM98501, shown on the cover

page of the datasheet, highlights the main features of the de-

vice: correlated double sampling (CDS), 0 dB–32 dB digitally

programmable gain amplifier (PGA), digital black level cor-

rection feedback loop, 8-bit DAC, analog clamp, bandgap

voltage reference, and a 10-bit, 27 MHz analog-to-digital

converter.

CORRELATED DOUBLE SAMPLING

Correlated double sampling (CDS) is a key feature in CCD

image processors. The sampling process consists of two

samples being taken for each pixel. The first stores the reset

voltage of the input pixel, and the second stores the video

signal amplitude. The two samples are subtracted from one

another, effectively removing the reset error offset of each

pixel. This sampling system operates at 27 MHz, allowing

the use of imagers that have resolution at high speeds. Op-

eration at these higher clock rates generates electronic im-

ages similar to a high-speed camera, preventing blearing of

the image caused by motion during the exposure.

DS101292-8

FIGURE 7. Digital Output Data Timing

DS101292-9

FIGURE 8. System Timing

LM98501CCVBH bảng dữ liệu(PDF) 13 Page - National Semiconductor (TI)