Broadcom

- 10 -

ACPL-33JT

Data Sheet

Thermal Resistance Model for ACPL-33JT

Thermal Resistance Model for ACPL-33JT

The diagram for measurement is shown in Figure 4. This is a multi chip package with four heat sources, the effect of heating of one

die due to the adjacent dice are considered by applying the theory of linear superposition. Here, one die is heated first and the

temperatures of all the dice are recorded after thermal equilibrium is reached. Then, the second die is heated and all the dice

temperatures are recorded and so on until the 4th die is heated. With the known ambient temperature, the die junction

temperature and power dissipation, the thermal resistance can be calculated. The thermal resistance calculation can be cast in

matrix form. This yields a 4 by 4 matrix for our case of four heat sources.

Figure 4 Diagram of ACPL-33JT for Measurement

Table 9 Package Characteristics

Parameter

Symbol

Min.

Typ.

Max.

Units

Test Conditions

Input-Output Momentary

Withstand Voltage

5000

Resistance (Input-Output)



Capacitance (Input-Output)

0.8

pF

f = 1 MHz