UT80C196 datasheet(15/42 Pages) AEROFLEX

15 / 42 page

P2.2

---

Port 2 Pin 2. An input only port pin that is written at location

10h of HWindow 0. P2.2 will always generate EXTINT1

(INT13, 203Ah) unless masked by the INT_MASK1 register.

Assert EXTINT1 for at least 2 state times to guarantee acknowl-

edgment by the interrupt controller.

EXTINT

High

External Interrupt. Setting IOC1.1 = 0 enables pin 15 as the

source for the external interrupt EXTINT. A rising edge on this

pin will generate EXTINT (INT07, 200Eh). Assert EXTINT for

at least 2 state times to ensure acknowledgment by the interrupt

controller.

During Power Down mode, asserting EXTINT places the chip

back into normal operation, even if EXTINT is masked.

TUBS

RESET

Low

Master Reset. The first external reset signal supplied to the

UT80C196KD must be active for at least 16 state times. All

subsequent RESET assertions need only be active for 1 state

time because the UT80C196KD will continue driving the

RESET signal for an additional 16 state times. See section 1.1.2

for more information on the RESET function of the

UT80C196KD.

P2.1

---

Port 2 Pin 1. An input only port pin that is read at location 10h

of HWindow 0.

Setting SPCON.3 = 0 enables the P2.1 function of pin 17.

RXD

---

RXD is a bidirectional serial data port. When operating in Serial

Modes 1, 2, and 3, RXD receives serial data. When using Serial

Mode 0, RXD operates as an input and an open-drain output for

data.

Setting SPCON.3 = 1 enables the RXD function of pin 17.

TUO

P2.0

---

Port 2 Pin 0. An output only port pin that is written at location

10h of HWindow 0.

Setting IOC1.5 = 0 enables the P2.0 function of pin 18.

TUO

TXD

---

Transmit Serial Data (TXD). When set to Serial Mode 1, 2, or 3,

TXD transmits serial port data. When using Serial Mode 0,

TXD is used as the Serial Clock output.

Setting IOC1.5 = 1 enables the TXD function of pin 18.

TUI

ICT

Low

In-Circuit Test. The UT80C196KD will enter the In-Circuit

Test mode if this pin is held low during the rising edge of

RESET.

Table 10: 68-lead Flat Pack Pin Descriptions

QFP Pin#

I/O

Name

Active

Description

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