AD7403

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER REQUIREMENTS

4.5

5.5

V

3

5.5

V

30

36

mA

12

18

mA

6

10

mA

Power Dissipation

231

297

mW

185

231

mW

1

2

See the Terminology section.

3

Not production tested. Sample tested during initial release to ensure compliance.

AD7403-8

tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective

ground.

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

STATIC PERFORMANCE

Resolution

16

Bits

Filter output truncated to 16 bits

Integral Nonlinearity (INL)2

±2

±6.5

LSB

Differential Nonlinearity (DNL)2

±0.99

LSB

Guaranteed no missed codes to 16 bits

Offset Error2

±1

±1.7

mV

Offset Drift vs. Temperature3

2

6.8

µV/°C

425

µV/V

Gain Error2

±0.2

±0.8

% FSR

±0.2

±1.4

% FSR

Gain Error Drift vs. Temperature3

32

80

ppm/°C

20

51

µV/°C

Gain Error Drift vs. VDD13

±0.2

mV/V

ANALOG INPUT

Input Voltage Range

−320

+320

mV

Full-scale range

−250

+250

mV

For specified performance

Input Common-Mode Voltage Range

−200 to +300

mV

Dynamic Input Current

±45

±50

µA

0.05

µA

DC Leakage Current

±0.01

±0.6

µA

Input Capacitance

14

pF

DYNAMIC SPECIFICATIONS

Signal-to-Noise-and-Distortion Ratio (SINAD)2

82

87

dB

Signal-to-Noise Ratio (SNR)2

86

88

dB

Total Harmonic Distortion (THD)2

−94

dB

Peak Harmonic or Spurious Noise (SFDR)2

−94

dB

Effective Number of Bits (ENOB)2

13.3

14.2

Bits

ISOLATION TRANSIENT IMMUNITY2

25

30

kV/µs

LOGIC INPUTS

CMOS with Schmitt trigger

V

V

±0.6

µA

10

pF

LOGIC OUTPUTS

V

0.4

V

Rev. B | Page 4 of 24