ADRF6820ACPZ-R7 datasheet(6/45 Pages) AD

tên linh kiện	ADRF6820ACPZ-R7

Giải thích chi tiết về linh kiện	Internal LO frequency range

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6 / 45 page

ADRF6820

Data Sheet

Rev. C | Page 6 of 45

DIGITAL LOGIC SPECIFICATIONS

Table 4.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Input Voltage High, VIH

1.4

Input Voltage Low, VIL

0.70

Output Voltage High, VOH

IOH = −100 µA

2.3

Output Voltage Low, VOL

IOL = 100 µA

0.2

Serial Clock Period

tSCLK

Setup Time Between Data and Rising Edge of SCLK

tDS

Hold Time Between Data and Rising Edge of SCLK

tDH

Setup Time Between Falling Edge of CS and SCLK

Hold Time Between Rising Edge of CS and SCLK

Minimum Period SCLK in a Logic High State

tHIGH

Minimum Period SCLK in a Logic Low State

tLOW

Maximum Time Delay Between Falling Edge of SCLK and Output Data Valid for

a Read Operation

tACCESS

231

Maximum Time Delay Between CS Deactivation and SDIO Bus Return to

High Impedance

Timing Diagram

tDS

tDH

tHIGH

tLOW

tSCLK

DON'T CARE

D15

D14

D13

DON'T CARE

SCLK

SDIO

R/W

tACCESS

Figure 2. Setup and Hold Timing Measurements

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