ADF4355BCPZ datasheet(31/36 Pages) AD

31 / 36 page

ADF4355

Data Sheet

Rev. A | Page 30 of 35

7. Wait >16 ADC_CLK_DIV cycles. For example, if

ADC_CLK_DIV = 99.417 kHz, wait 16/99417 sec =

161 µs. See the Register 10 section.

8. Register 0 (autocalibration enabled [DB21 = 1]).

For fPFD > 75 MHz (initially lock with half fPFD), use the

following sequence:

1. Register 10.

2. Register 4 (counter reset enabled [DB4 = 1]).

3. Register 2 (for halved fPFD).

4. Register 1 (for halved fPFD).

5. Register 0 (for halved fPFD; autocalibration disabled).

6. Register 4 (counter reset disabled [DB4 = 0])

7. Wait >16 ADC_CLK cycles. For example, if

ADC_CLK = 99.417 kHz, wait 16/99417 sec = 161 μs.

See the Register 10 section for more information.

8. Register 0 (for halved fPFD; autocalibration enabled).

9. Register 2 (for desired fPFD).

10. Register 1 (for desired fPFD).

11. Register 0 (for desired fPFD; autocalibration disabled).

The frequency change only occurs when writing to Register 0.

RF SYNTHESIZER—A WORKED EXAMPLE

Use the following equations to program the ADF4355 synthesizer:

RFOUT =

MOD1

MOD2

FRAC2

FRAC1

INT

× (fPFD)/RF Divider

(7)

where:

RFOUT is the RF frequency output.

INT is the integer division factor.

FRAC1 is the fractionality.

FRAC2 is the auxiliary fractionality.

MOD2 is the auxiliary modulus.

MOD1 is the fixed 24-bit modulus.

RF Divider is the output divider that divides down the VCO

frequency.

fPFD = REFIN × ((1 + D)/(R × (1 + T)))

(8)

where:

REFIN is the reference frequency input.

D is the RF REFIN doubler bit.

R is the RF reference division factor.

T is the reference divide by 2 bit (0 or 1).

For example, in a universal mobile telecommunication system

(UMTS) where 2112.8 MHz RF frequency output (RFOUT) is

required, a 122.88 MHz reference frequency input (REFIN) is

available. Note that the ADF4355 VCO operates in the frequency

range of 3.4 GHz to 6.8 GHz. Therefore, an RF divider of 2 must

be used (VCO frequency = 4225.6 MHz, RFOUT = VCO frequency/

RF divider = 4225.6 MHz/2 = 2112.8 MHz).

The feedback path is also important. In this example, the VCO

output is fed back before the output divider (see Figure 43).

In this example, divide the 122.88 MHz reference signal by 2 to

generate a fPFD of 61.44 MHz. The desired channel spacing is

200 kHz.

fPFD

PFD

VCO

DIVIDER

÷2

RFOUT

Figure 43. Loop Closed Before Output Divider

The worked example is as follows:

•

N = VCOOUT/fPFD = 4225.6 MHz/61.44 MHz =

68.7760416666666667

•

INT = int(VCO frequency/fPFD) = 68

•

FRAC = 0.7760416666666667

•

MOD1 = 16,777,216

•

FRAC1 = int(MOD1 × FRAC) = 13019817

•

Remainder = 0.6666666667 or 2/3

•

MOD2 = fPFD/GCD(fPFD/fCHSP) = 61.44

MHz/GCD(61.44 MHz/200 kHz) = 1536

•

FRAC2 = remainder × 1536 = 1024

From Equation 8,

fPFD = (122.88 MHz × (1 + 0)/2) = 61.44 MHz

(9)

From Equation 7,

2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +

FRAC2/MOD2)/224))/2

(10)

where:

INT = 68

FRAC1 = 13,019,817

FRAC2 = 1024

MOD2 = 1536

RF Divider = 2 (see Equation 7)

REFERENCE DOUBLER AND REFERENCE DIVIDER

The on-chip reference doubler allows the input reference signal

to be doubled. The doubler is useful for increasing the PFD

comparison frequency. To improve the noise performance of

the system, increase the PFD frequency. Doubling the PFD

frequency usually improves noise performance by 3 dB.

The reference divide by 2 divides the reference signal by 2,

resulting in a 50% duty cycle PFD frequency.

SPURIOUS OPTIMIZATION AND FAST LOCK

Narrow loop bandwidths can filter unwanted spurious signals,

but these bandwidths usually have a long lock time. A wider

loop bandwidth achieves faster lock times but may lead to

increased spurious signals inside the loop bandwidth.

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