ADA4350ARUZ-R7 datasheet(14/38 Pages) AD

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Data Sheet

ADA4350

Rev. B | Page 13 of 37

TIMING SPECIFICATIONS

All input signals are specified with tR = tF = 2 ns (10% to 90% of DVDD) and timed from a voltage threshold level of VTH = 1.3 V at

DVDD = 3.3 V or VTH =1.7 V at DVDD = 5 V. Guaranteed by characterization; not production tested. See Figure 2 and Figure 3.

Table 9.

DVDD = 3.3 V

DVDD = 5 V

Parameter

Description1

Min

Max

Min

Max

Unit

SCLK period.

SCLK positive pulse width.

SCLK negative pulse width.

CS setup time. The time required to begin sampling data after CS goes low.

CS hold time. The amount of time required for CS to be held low after the last data bit

is sampled before bringing CS high. Data is latched on the CS rising edge. If LATCH is

held low, data is also applied on the CS rising edge.

CS positive pulse width. The amount of time required between consecutive words.

Data setup time. The amount of time the data bit (SDI) must be set before sampling

on the falling edge of SCLK.

Data hold time. The amount of time SDI must be held after the falling edge of SCLK

for valid data to be sampled.

Data latched to the internal switches updated. The amount of time it takes from the

latched data being applied until the internal switches are updated.

145

140

LATCH disabled referenced from the rising edge of CS.

LATCH enabled referenced from the falling edge of LATCH.

t10

LATCH negative pulse width.

t112

SCLK rising edge to SDO valid. The amount of time between the SCLK rising edge

and the valid SDO transitions (CLSDO3 = 20 pF).

t12

CS rising edge to the SCLK falling edge. The amount of time required to prevent a

25th SCLK edge from being recognized (only 24 bits allowed for valid word).

When referring to a single function of a multifunction pin, only the portion of the pin name that is relevant to the specification is listed. For full pin names of

multifunction pins, refer to the Pin Configuration and Function Descriptions section.

This is while in daisy-chain mode and in readback mode.

CLSDO is the capacitive load on the SDO output.

Timing Diagrams for Serial Mode

t10

SCLK

SDI

INTERNAL

SWITCHES

POSITION

SWITCHES

UPDATED

INTERNAL

SWITCHES

POSITION

SWITCHES

UPDATED

LATCH

VTH

LATCH ENABLED: LATCHED DATA APPLIED ON FALLING EDGE OF LATCH

LATCH DISABLED: DATA LATCHED AND APPLIED ON RISING EDGE OF CS

Figure 2. Write Operation

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