For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

26

HMC702LP6CE

v10.0812

14 GHz 16-BIT FRACTIONAL-N PLL

Serial Port WRITE Operation

aVDD = DVDD = 3V ±10%, aGnD = DGnD = 0V

Table 4. Timing Characteristics

Parameter

Conditions

Min.

Typ.

Max

Units

SEn to ScLK setup time

8

nsec

SDi to ScLK setup time

10

nsec

SDi to cLK hold time

10

nsec

ScLK high duration

8

nsec

ScLK low duration

8

nsec

SEn High duration

640

nsec

SEn low duration

20

nsec

a typical WritE cycle is shown in Figure 19.

a. the Master (host) both asserts SEn (Serial Port Enable) and clears SDi to indicate a WritE

cycle, followed by a rising edge of ScLK.

b. the slave (synthesizer) reads SDi on the 1st rising edge of ScLK after SEn. SDi low initiates

the WritE cycle (/Wr)

c. Host places the six address bits on the next six falling edges of ScLK, MSB first.

d. Slave registers the address bits in the next six rising edges of ScLK (2-7).

e. Host places the 24 data bits on the next 24 falling edges of ScK, MSB first .

f. Slave registers the data bits on the next 24 rising edges of ScK (8-31).

g. SEn is de-asserted on or after the 32nd falling edge of ScLK.

Figure 19. Serial Port Timing Diagram - WRITE

LD status always:

reg2h[1:0] = 11

reg1ah[13:12] = 01

High impedance always:

reg2h[1:0] = 10

reg1ah[13:12] = xx (x=don’t care)

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