2.3 R0 REGISTER

Reg

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9876543210

DATA[20:0]

C2

C1

C0

R0

000

IF_

RST

IF_

CP

IF_

CPP

IF_R[14:0]

0

0

0

2.3.1 IF_R[14:0] — R Divider Ratio, IF Synthesizer

The R0 control word is used to configure the 15 Bit R Divider for the IF Synthesizer. Divide ratios ranging from 3 to 32,767 are

supported.

IF_R[14:0]

Divide

Ratio

14

13

12

11

10

987654321

0

3

00000000000001

1

4

00000000000010

0

•

••••••••••••••

•

32,767

11111111111111

1

2.3.2 IF_CPP — Charge Pump Polarity, IF Synthesizer

This bit controls the polarity of phase detector for the IF synthesizer. It should be set to “1” when the IF VCO has positive tuning

gain, and “0” when the tuning gain is negative.

2.3.3 IF_CP — Charge Pump Gain, IF Synthesizer

This bit controls the charge pump gain for the IF Synthesizer. Set this bit to 0 for low gain mode (100 uA) and a 1 for high gain

mode (800 uA). When FastLock mode is enabled, the charge pump gain is controlled by the FastLock circuit.

2.3.4 IF_RST — Counter Reset, IF Synthesizer

The IF Counter Reset enable bit when activated (IF_RST = 1) allows the reset of both the IF N and R dividers and sets the IF

counter. The maximum error is one prescaler cycle.

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