PRELIMINARY SPECIFICATION

64COM/128SEG DRIVE FOR DOT MATRIX LCD

KS0708

9

M/M-96-D001

97-09-19

Busy flag

Busy flag indicates whether KS0708 is operating or not. When busy flag is high, KS0708 is in internal oper-

ation. When low, KS0708 can accept the data or instruction. DB7 indicates busy flag of the KS0708.

E

BUSY FLAG

Figure 1. Busy timing

Display Timing Generator Circuit

This section explains how the timing generation circuit operates.

- Signal generation to display start line counter and display data latch circuit.

- The display clock(CLK2) generates a clock to the line counter. The display start line address of

the display RAM is synchronized with the display clock. 128-bit display data is latched by the

display data latch circuit in synchronization with the display clock and output to the segment LCD

drive output pin.

- LCD AC signal(M) generation.