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UPSD323X bảng dữ liệu(PDF) 84 Page - STMicroelectronics

tên linh kiện UPSD323X
Giải thích chi tiết về linh kiện  Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
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UPSD323X bảng dữ liệu(HTML) 84 Page - STMicroelectronics

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Special Function Register for the DDC Interface
There are eight SFR in the DDC interface:
RAMBUF, DDCCON, DDCADR, DDCDAT are
DDC registers.
S1CON, S1STA, S1DAT, S1ADR are I2C Inter-
face registers, same as the ones described in the
standalone I
2C bus.
DDCDAT Register. DDC1
DATA
register for
transmission (DDCDAT: 0D5H)
s
8-bit READ and WRITE register.
s
Indicates DATA BYTE to be transmitted in
DDC1 protocol.
DDCADR Register. Address pointer for DDC in-
terface (DDCADR: 0D6H)
s
8-bit READ and WRITE register.
s
Address pointer with the capability of the post
increment. After each access to RAMBUF
register (either by software or by hardware
DDC1 interface), the content of this register will
be increased by one. It’s available both in
DDC1, DDC2 (DDC2B, DDC2B+, and
DDC2AB) and system operation.
Table 60. DDC SFR Memory Map
SFR
Addr
Reg
Name
Bit Register Name
Reset
Value
Comments
76
5
4
3
2
1
0
D4
RAMBUF
XX
DDC Ram
Buffer
D5
DDCDAT
00
DDC Data
xmit register
D6
DDCADR
00
Addr pointer
register
D7 DDCCON
—
EX_DAT SWENB DDC_AX DDCINT DDC1EN SWHINT
M0
00
DDC Control
Register



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