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UPSD323X bảng dữ liệu(PDF) 83 Page - STMicroelectronics

tên linh kiện UPSD323X
Giải thích chi tiết về linh kiện  Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
PDF  176 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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UPSD323X bảng dữ liệu(HTML) 83 Page - STMicroelectronics

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µPSD323X
DDC INTERFACE
The basic DDC unit consists of an I2C interface
and 256 bytes of SRAM for DDC data storage. The
8032 core is responsible of loading the contents of
the SRAM with the DDC data. The DDC unit has
the following features:
s
Supports both DDC1 and DDC2b Modes.
s
Features 256 bytes of DDC data - initialized by
the 8032
s
Supports fully automatic operation of DDC1 and
DDC2b Modes
s
DDC operates in Slave Mode only.
s
SW Interrupt Mode available (existing design)
The interface signals for the DDC can be mapped
to pins in Port 4. The interface consists of the stan-
dard VSYNC (P4.2), SDA (P4.0) and SCL (P4.1)
DDC signals. The conceptual block diagram is il-
lustrated in Figure 43.
Figure 40. DDC Interface Block Diagram
AI06628
INT
DDCCON
INTR (from SISTA)
Initialization Synchronization
DDCADR
Address Pointer
RAM
Buffer
RAMBUF
VSYNCEN
DDC1 Transmitter
DDCDAT
DDC1 Hold Register
DDC1/DDC2
Detection
SISTA
SICON
SCL1
SDA1
Bus Clock Generator
Arbitration Logic
S1DAT
S1ADR1
S1ADR0
Shift Register
DDC2B/DDC2AB
DDC2B+Interface
Monitor Address
Monitor Address
10
XX
EX_
DAT
SW
ENB
DDC1
INT
DDC1
EN
SWH
INT
M0



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