MLX71122_16 datasheet(23/59 Pages) MELEXIS

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MLX71122

300 to 930MHz FSK/FM/ASK Receiver

Datasheet

REVISION 014 – AUGUST, 2016

Page 23 of 59

390 10 71122 01

Fig. 6

Pulse Swallow Divider Timing

Therefore the overall feedback divide ratio is:

























(16)

Further restrictions can be derived from above equation: A < P and A < N.

Some math shows that for uniform frequency steps without gaps (N ≥ P) the following condition is

necessary:









(17)

3.2.2. PLL Counter Ranges

In order to cover the frequency range of about 300 to 930MHz the following counter values are

implemented in the receiver:

PLL Counter Ranges

0 to 31 (5bit)

3 to 2047 (11bit)

Therefore the minimum and maximum divider ratios for uniform frequency steps are given by:

1024

totmin







65535

2047

totmax









3.2.3. Reference Oscillator (RO)

The reference oscillator is based on a Colpitts topology with two

integrated functional capacitors as shown in figure 7. The circuitry is

optimized for a load capacitance range of 10pF to 15pF. The equivalent

input capacitance CRO offered by the oscillator input pin ROI is about

15pF. To ensure a fast and reliable start-up and a very stable frequency

over the specified supply voltage and temperature range, the oscillator

bias circuitry provides an amplitude regulation. Via SPI it is possible to

adjust the typical core current with register ROCUR. There are four

values available (see 4.1.7). At the default setting 355A, the

amplitude at pin ROI is monitored in order to regulate the current of

the oscillator core IRO.

Fig.7:

RO schematic

A cycles of

(N-A) cycles of

period of

30pF

XTAL

ROI

VCC

30pF

VEE

IRO

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