BLUENRG-1 datasheet(23/173 Pages) STMICROELECTRONICS

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BlueNRG-1

Functional details

DocID028866 Rev 1

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uint32_t fsm_status;

uint16_t cnt_time = 0;

do {

cnt_time++;

fsm_status = 0x00004382;

BLUE_CTRL->RADIO_CONFIG = 0x10000 | (uint16_t) ( (

(uint32_t)(&fsm_status) ) & 0x0000FFFF);

while((BLUE_CTRL->RADIO_CONFIG & 0x10000) !=

0);

} while(((fsm_status>>16) != 0x05) &&

(cnt_time<1000));

After switching to active state (and not before), write 0x15 in the COMMAND register

of AHBUPCONV peripheral.

Around 10 system clock cycles after this last write, the system will run at 32 MHz except for

specific blocks requiring a fixed 16 MHz.

The application can make the bus and the core run to 16 MHz by writing 0x14 in

the COMMAND register of AHBUPCONV peripheral.

3.5.4

Clock and reset registers

CKGEN_SOC peripheral base address (CKGEN_SOC_BASE_ADDR) 0x40900000.

Table 10: CKGEN_SOC registers

Address

offset

Name

Reset

Description

0x00

CONTROL

0x01FA03F0

Control clock and Reset of SOC. Refer to the

detailed description below.

0x08

REASON_RST

0x00000000

Indicates the Reset reason from Cortex-M0.

Refer to the detailed description below.

0x1C

DIE_ID

0x00000110

Identification information of the device. Refer

to the detailed description below.

0x20

CLOCK_EN

0x0003FFFF

Enable or gates the APB clock of the

peripherals. Refer to the detailed description

below.

0x24

DMA_CONFIG

0x00000000

DMA config. Refer to the detailed description

below.

Table 11: CKGEN_SOC - CONTROL register description: address offset

CKGEN_SOC_BASE_ADDR+0x00

Bit

Field name

Reset

Description

9:0

RESERVED

0x3F0

RESERVED

13:10

UART_CKDIV

0x0

UART baud rate clock setting from 1 to 16 MHz according

to the formula 16 / (n + 1) MHz.

31:14

RESERVED

0x007E8

RESERVED

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