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BLUENRG-1 bảng dữ liệu(PDF) 22 Page - STMicroelectronics |
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BLUENRG-1 bảng dữ liệu(HTML) 22 Page - STMicroelectronics |
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22 / 173 page ![]() Functional details BlueNRG-1 22/173 DocID028866 Rev 1 3.5.1.2 Watchdog reset The BlueNRG-1 contains a watchdog timer, which may be used to recover from software crashes. The watchdog contains a 32-bit down counter, which generates an interrupt, if the interrupt is not serviced, the watchdog will generate a reset. The watchdog Reset will Reset the Flash controller, the Cortex-M0 and all its peripherals but it will not Reset the debug circuitry of the Cortex-M0. 3.5.1.3 System reset request The system reset request is generated by the debug circuitry of the Cortex-M0. The debugger writes to the SYSRESETREQ bit of the “Application Interrupt and Reset Control Register” (AIRCR). This system reset request through AIRCR register can also be done by embedded software. The system reset request does not affect the debugger, thus allowing the debugger to remain connected during the reset sequence. 3.5.1.4 Lockup reset The Cortex-M0 generates an output LOCKUP that indicates that the core is in the architected lock-up state resulting from an unrecoverable exception. The LOCKUP signal is used to generate reset in the BlueNRG-1. This reset will affect the Cortex-M0, the Flash controller, and all the peripherals. The LOCKUP signal does not Reset the Cortex-M0 debug circuitry. 3.5.2 Reset and wakeup reason decoding The BlueNRG-1 provides a set of registers to identify the reason behind a reset and wakeup generation. Two registers are used: CKGEN_SOC->REASON_RST and CKGEN_BLE->REASON_RST. The possible reasons are listed below: 1. If the register CKGEN_SOC->REASON_RST = 0, according to the CKGEN_BLE- >REASON_RST the possible reasons are: a. Wakeup from IO9, IO10, IO11, IO12, IO13. b. Wakeup from internal timer: BLE timer 1 or BLE timer 2. c. POR or BOR 2. If the register CKGEN_SOC->REASON_RST is not 0, according to its value the possible reasons are: a. System reset b. Watchdog reset c. Lockup reset. 3.5.3 Switching to external clock When the system is in preactive state (run from internal RO 16 MHz), the software sequence to switch to active should include switch to external XO. When the system uses an external XO at 32 MHz instead of 16 MHz, the following steps need to be done: 1. In preactive state, operate as follow routine: uint8_t config[] = { 0x02, 0x3A, 0x44, 0x00}; BLUE_CTRL->RADIO_CONFIG = 0x10000 | (uint16_t) ( (uint32_t)config & 0x0000FFFF ); while((BLUE_CTRL->RADIO_CONFIG & 0x10000) != 0); 1. Set the bitfield MHZ32_SEL of register SYSTEM_CTRL, for the digital part. 2. Wait the state machine is in active state by using the follow routine: |
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