SST49LF080A datasheet(11/50 Pages) MICROCHIP

11 / 50 page

DS20005086B

11/14

8 Mbit LPC Flash

SST49LF080A

Data Sheet

Figure 5: LPC Read Cycle Waveform

Table 5: LPC Read Cycle

Clock

Cycle

Field

Name

Field

Contents

LAD[3:0]1

LAD[3:0]

Direction

Comments

START

0000

LFRAME# must be active (low) for the part to respond.

Only the last start field (before LFRAME# transitions

high) should be recognized.

CYCTYPE

+ DIR

010X

Indicates the type of cycle. Bits 3:2 must be “01b” for memory

cycle. Bit 1 indicates the type of transfer “0” for Read. Bit 0 is

reserved.

3-10

ADDRESS

YYYY

Address Phase for Memory Cycle. LPC protocol sup-

ports a 32-bit address phase. YYYY is one nibble of the

entire address. Addresses are transferred most-signifi-

cant nibble fist. See Table 3 for address bits definition

and Table 4 for valid memory address range.

TAR0

1111

then Float

In this clock cycle, the host has driven the bus to all 1s

and then floats the bus. This is the first part of the bus

“turnaround cycle.”

TAR1

1111 (float)

Float

then OUT

The SST49LF080A takes control of the bus during this

cycle

SYNC

0000

OUT

The SST49LF080A outputs the value 0000b indicating

that data will be available during the next clock cycle.

DATA

ZZZZ

OUT

This field is the least-significant nibble of the data byte.

DATA

ZZZZ

OUT

This field is the most-significant nibble of the data byte.

TAR0

1111

OUT

then Float

In this clock cycle, the SST49LF080A has driven the bus

to all 1s and then floats the bus. This is the first part of

the bus “turnaround cycle.”

TAR1

1111 (float)

Float

then IN

The host takes control of the bus during this cycle

T5.0 25026

1. Field contents are valid on the rising edge of the present clock cycle.

1235 F04.0

LCLK

CE#

LFRAME#

LAD[3:0]

0000b

010Xb

A[23:20] A[19:16]

A[3:0]

A[7:4]

A[11:8]

A[15:12]

1111b

Tri-State

2Clocks

TAR0

Load Address in 8 Clocks

Address

1Clock 1Clock

Start

CYCTYPE

DIR

TAR

1Clock

Sync

Data

Data Out 2 Clocks

0000b

D[7:4]

D[3:0]

A[31:28] A[27:24]

TAR1

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