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SST49LF080A bảng dữ liệu(PDF) 10 Page - Microchip Technology

tên linh kiện SST49LF080A
Giải thích chi tiết về linh kiện  8 Mbit LPC Flash
PDF  50 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
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SST49LF080A bảng dữ liệu(HTML) 10 Page - Microchip Technology

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©2014 Silicon Storage Technology, Inc.
DS20005086B
11/14
10
8 Mbit LPC Flash
SST49LF080A
Data Sheet
INIT#, RST#
AVIL on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function
internally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper
CPU initialization. During a Read operation, driving INIT# or RST# pins low deselects the device
and places the output drivers, LAD[3:0], in a high-impedance state. The reset signal must be held
low for a minimal duration of time TRSTP. A reset latency will occur if a reset procedure is performed
during a Program or Erase operation. See Table 19, Reset Timing Parameters for more informa-
tion. A device reset during an active Program or Erase will abort the operation and memory con-
tents may become invalid due to data being altered or corrupted from an incomplete Erase or
Program operation.
System Memory Mapping
The LPC interface protocol has address length of 32-bit or 4 GByte. The SST49LF080A will
respond to addresses in the range as specified in Table 4.
Refer to “Multiple Device Selection” section for more detail on strapping multiple SST49LF080A
devices to increase memory densities in a system and “Registers” section on valid register
addresses.
Table 4: Address Decoding Range
ID Strapping
Device Access
Address Range
Memory Size
Device #0 - 3
Memory Access
FFFF FFFFH : FFC0 0000H
4 MByte
Register Access
FFBF FFFFH : FF80 0000H
4 MByte
Device #4 - 7
Memory Access
FF7F FFFFH : FF40 0000H
4 MByte
Register Access
FF3F FFFFH : FF00 0000H
4 MByte
Device #8 - 11
Memory Access
FEFF FFFFH : FEC0 0000H
4 MByte
Register Access
FEBF FFFFH : FE80 0000H
4 MByte
Device #12 - 15
Memory Access
FE7F FFFFH : FE40 0000H
4 MByte
Register Access
FE3F FFFFH : FE00 0000H
4 MByte
Device #01
1. For device #0 (Boot Device), SST49LF080A decodes the physical addresses of the top 2 blocks (including Boot
Block) both at
system memory ranges FFFF FFFFH to FFFE 0000H and 000F FFFFH to 000E 0000H.
Memory Access
000F FFFFH : 000E 0000H
128 KByte
T4.0 25026



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