PC87373 datasheet(112/174 Pages) NSC

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8.0 Fan Speed Monitor (Continued)

112

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8.3 FAN SPEED MONITOR REGISTERS

The following abbreviations are used to indicate the Register Type:

R/W

= Read/Write.

= Read from register (write to the same address is to a different register).

= Write (see above).

= Read Only.

= Write Only. Reading from the bit returns 0.

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect.

8.3.1

Fan Speed Monitor Register Map

8.3.2

Fan Speed Monitor Threshold Low Register (FMTHRL)

This register holds the low byte (bits 7-0) of the lowest permitted fan speed value. It is reset to FFh.

Power Well: VDD3

Location:

Device specific

Type:

R/W

Table 42. Fan Speed Monitor Register Map

Offset

Mnemonic

Type

Power Well

Section

Device speciﬁc1

1. The location of this register is defined in Section 3.15.1 on page 67.

FMTHRL

Fan Speed Monitor Threshold Low

R/W

VDD3

8.3.2

Device speciﬁc1

FMTHRH

Fan Speed Monitor Threshold High

R/W

VDD3

8.3.3

Device speciﬁc1

FMSPRL

Fan Speed Monitor Speed Low

VDD3

8.3.4

Device speciﬁc1

FMSPRH

Fan Speed Monitor Speed High

VDD3

8.3.5

Device speciﬁc1

FMCSR

Fan Speed Monitor Control and Status

Varies per bit

VDD3

8.3.6

Bit

43210

Name

THRSH_LOW

Reset

11111

Bit

Description

7-0

THRSH_LOW (Fan Speed Threshold Value - Low). This ﬁeld contains the low byte of the threshold setting,

indicating the lowest permitted fan speed value. If the number of clock cycles counted in one fan revolution is

higher than the THRSH value, OVR_THR bit is set in FMCSR register and the FAN_SPD data is “frozen” at its

last value. In addition, an interrupt (if enabled) is issued.

To prevent unpredictable results, the contents of this register can only be changed when the corresponding

FANMON_EN bit in FSCMCF1 or FSCMCF2 register is reset to 0 (see Section 3.15.3 on page 68 and Section

3.15.4 on page 69).

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