PC87373 datasheet(108/174 Pages) NSC

108 / 174 page

7.0 Fan Speed Control (Continued)

108

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7.3 FAN SPEED CONTROL REGISTERS

The following abbreviations are used to indicate the Register Type:

R/W

= Read/Write.

= Read from a speciﬁc register (write to the same address is to a different register).

= Write (see above).

= Read Only.

= Write Only. Reading from the bit returns 0.

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect.

7.3.1

Fan Speed Control Register Map

7.3.2

Fan Speed Control Pre-Scale Register (FCPSR)

This register controls the clock of the PWM counter. It is reset by hardware to 00h.

Note: The contents of this register must not be changed when the corresponding FANCTL_EN bit in FSCMCF1 or

FSCMCF2 register is set (see Section 3.15.3 on page 68), as this may produce unpredictable results.

Power Well: VDD3

Location:

Device specific

Type:

R/W

Table 40. Fan Speed Control Register Map

Offset

Mnemonic

Type

Power Well

Section

Device speciﬁc1

1. The location of this register is defined in Section 3.15.1 on page 67.

FCPSR

Fan Speed Control Pre-Scale

R/W

VDD3

7.3.2

Device speciﬁc1

FCDCR

Fan Speed Control Duty Cycle

R/W

VDD3

7.3.3

Bit

43210

Name

CLK_SEL

PRE-SCALE

Reset

00000

Bit

Description

CLK_SEL (Clock Select). This bit selects the input clock for the clock divider.

0: 24 MHz (default)

1: 200 KHz

6-0

PRE-SCALE (Pre-Scale Value). The clock divider for the input clock (24 MHz or 200 KHz) is PRE-SCALE + 1.

Writing 0000000b (default) to these bits transfers the input clock directly to the counter. The maximum clock

divider is 124 (7Bh +1). These bits must not be programed with the values 7Ch, 7Dh, 7Eh and 7Fh as this may

produce unpredictable results.

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