LE25S161 datasheet(17/54 Pages) ONSEMI

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LE25S161

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10-2. Write Status Register (WRSR)

The information in status registers BP0, BP1, BP2, TB and SRWP can be rewritten using this command. bit0 ( RDY), bit1

(WEN) and bit6 (SUS) are read-only bits and cannot be rewritten. The information in bits BP0, BP1, BP2, TB and SRWP

is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at power-down.

"Figure 3. Write Status Register (WRSR)" shows the timing waveforms.

"Figure 31. Write Status Register Flowcharts" shows the flowcharts.

The sequence of WRSR operation :

CS goes to low  input WRSR command (01h)

 Status Register data input on SI

 CS goes to high (be executed by the rising CS edge)

Erase and program are performed automatically inside the device by Write Status Register. So that erasing or other

processing is unnecessary before executing the command. By the operation of this command, the information in bits BP0,

BP1, BP2, TB and SRWP can be rewritten. Since bits bit0 (RDY), bit1 (WEN), bit 6 (SUS) of the status register cannot be

written, no problem will arise if an attempt is made to set them to any value when rewriting the status register. Write

Status Register ends can be detected by RDY of Read Status Register (RDSR). To initiate Write Status Register, the logic

level of the WP pin must be set high and status register WEN must be set to "1".

tWRSR

Self-timed

Write Cycle

SCK

High Impedance

DATA

01h

Mode3

Mode0

8CLK

MSB

Figure 3. Write Status Register (WRSR)

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