CS8415A-CS datasheet(27/42 Pages) CIRRUS

27 / 42 page

CS8415A

8.16

Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only)

The following 10 registers contain the decoded Q-channel subcode data

Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus bit 7 of address 14h is Q[0]

while bit 0 of address 0Eh is Q[7]. Similarly bit 0 of address 1Dh corresponds to Q[79].

8.17

OMCK/RMCK Ratio (1Eh) (Read Only)

This register allows the calculation of the incoming sample rate by the host microcontroller from the

equation ORR=Fso/Fsi. The Fso is determined by OMCK, whose frequency is assumed to be 256

Fso. ORR is represented as an unsigned 2-bit integer and a 6-bit fractional part. The value is mean-

ingful only after the PLL has reached lock. For example, if the OMCK is 12.288MHz, Fso would be

48KHz (48KHz = 12.288MHz/256). Then if the input sample rate is also 48KHz, you would get 1.0

from the ORR register.(The value from the ORR register is hexadecimal, so the actual value you will

get is 40h). If FSO/FSI > 3

63/

64, ORR will saturate at the value FFh. Also, there is no hysteresis on

ORR. Therefore a small amount of jitter on either clock can cause the LSB ORR[0] to oscillate.

ORR7:6 - Integer part of the ratio (Integer value=Integer(SRR[7:6]))

ORR5:0 - Fractional part of the ratio (Fraction value=Integer(SRR[5:0])/64)

8.18

C-bit or U-bit Data Buffer (20h - 37h)

Either channel status data buffer E or user data buffer E is accessible through these register addresses.

8.19

CS8415A I.D. and Version Register (7Fh) (Read Only)

ID3:0 - ID code for the CS8415A. Permanently set to 0100

VER3:0 - CS8415A revision level. Revision A is coded as 0001

CONTROL

ADDRESS

TRACK

INDEX

MINUTE

SECOND

FRAME

ZERO

ABS MINUTE

ABS SECOND

ABS FRAME

ORR7

ORR6

ORR5

ORR4

ORR3

ORR2

ORR1

ORR0

ID3

ID2

ID1

ID0

VER3

VER2

VER1

VER0

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