công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

CS8415A-CS bảng dữ liệu(PDF) 16 Page - Cirrus Logic

tên linh kiện CS8415A-CS
Giải thích chi tiết về linh kiện  96 kHz DIGITAL AUDIO INTERFACE RECEIVER
PDF  42 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS8415A-CS bảng dữ liệu(HTML) 16 Page - Cirrus Logic

Back Button CS8415A-CS Datasheet HTML 12Page - Cirrus Logic CS8415A-CS Datasheet HTML 13Page - Cirrus Logic CS8415A-CS Datasheet HTML 14Page - Cirrus Logic CS8415A-CS Datasheet HTML 15Page - Cirrus Logic CS8415A-CS Datasheet HTML 16Page - Cirrus Logic CS8415A-CS Datasheet HTML 17Page - Cirrus Logic CS8415A-CS Datasheet HTML 18Page - Cirrus Logic CS8415A-CS Datasheet HTML 19Page - Cirrus Logic CS8415A-CS Datasheet HTML 20Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 42 page
background image
CS8415A
16
routed to both the left and right data fields on SD-
OUT. Similarly, sub-frame B data will be routed to
both the left and right data fields of the next word
clock cycle of SDOUT.
Using mono mode is only necessary if the serial
audio output port must run at 96 kHz. If the
CS8415A is kept in normal stereo mode, and re-
ceives AES3 data arranged in mono mode, then
the serial audio output port will run at 48 kHz, with
left and right data fields representing consecutive
audio samples.
RCBL
Out
VLRCK
C, U
Ouput
RCBL and C output are only available in hardware mode.
RCBL goes high 2 frames after receipt of a Z pre-amble, and is high for 16 frames.
VLRCK is a virtual word clock, which may not exist, but is used to illustrate the CU timing.
VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate.
If the serial audio output port is in master mode, VLRCK = OLRCK.
If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required.
C, U transitions are aligned within 1% of VLRCK period to VLRCK edges
±
Figure 7. AES3 Receiver Timing for C & U pin output data



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com