CS8415A-CS datasheet(26/42 Pages) CIRRUS

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CS8415A

will not affect the RERR pin, will not affect the RERR interrupt, and will not affect the current audio sample. The

CCRC and QCRC bits behave differently from the other bits: they do not affect the current audio sample even when

unmasked. This register defaults to 00h.

8.14

Channel Status Data Buffer Control (12h)

BSEL - Selects the data buffer register addresses to contain User data or Channel Status data

Default = ‘0’

0 - Data buffer address space contains Channel Status data

1 - Data buffer address space contains User data

CBMR - Control for the first 5 bytes of channel status “E” buffer

Default = ‘0’

0 - Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data

1 - Prevent D to E buffer transfers from overwriting first 5 bytes of channel status data

DETCI - D to E C-data buffer transfer inhibit bit.

Default = ‘0’

0 - Allow C-data D to E buffer transfers

1 - Inhibit C-data D to E buffer transfers

CAM - C-data buffer control port access mode bit

Default = ‘0’

0 - One byte mode

1 - Two byte mode

CHS - Channel select bit

Default = ‘0’

0 - Channel A information is displayed at the EMPH pin and in the receiver channel status reg-

ister. Channel A information is output during control port reads when CAM is set to 0 (One

Byte Mode)

1 - Channel B information is displayed at the EMPH pin and in the receiver channel status reg-

ister. Channel B information is output during control port reads when CAM is set to 0 (One

Byte Mode)

8.15

User Data Buffer Control (13h)

DETUI - D to E U-data buffer transfer inhibit bit (valid in block mode only).

Default = ‘0’

0 - Allow U-data D to E buffer transfers

1 - Inhibit U-data D to E buffer transfers

BSEL

CBMR

DETCI

CAM

CHS

DETUI

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