VDP3133Y datasheet(38/76 Pages) MICRONAS

38 / 76 page

VDP 313xY

ADVANCE INFORMATION

Micronas

w v

PLL2/3 filter coefficients, 1of5 bit code

(n+ set bit number)

bit[5:0]

proportional coefficient PLL3, 2−n−1

bit[5:0]

proportional coefficient PLL2, 2−n−1

bit[5:0]

integral coefficient PLL2, 2−n−5

PKP3

PKP2

PKI2

w/r

horizontal drive and vertical signal control register

bit[5:0]

0..63

horizontal drive pulse duration in

µs (internally limited to 4..61)

bit[6]

0/1

disable/enable horizontal PLL2

and PLL3

bit[7]

0/1

1: disable horizontal drive pulse

during flyback

bit[8]

0/1

reserved, set to ’0’

bit[9]

0/1

enable/disable ultra black

blanking

bit[10]

0/1

0: all outputs blanked

1: normal mode

bit[11]

0/1

enable/disable clamping for

analog RGB input

bit[12]

0/1

disable/enable vertical free

running mode (FIELD is set to

field2, no interlace)

bit[13]

0/1

enable/disable vertical protection

bit[14]

reserved (set to 0)

bit[15]

0/1

disable/enable phase shift of

display clock

HVC

HDRV

EHPLL

EFLB

DUBL

EBL

DCRGB

SELFT

DVPR

DISKA

w/r

sync output control

bit[0]

invert INTLC

bit[1]

disable INTLC (tristateINTLC output)

bit[2]

invert VS

bit[3]

disable VS

bit[4]

disable CSY

bit[5]

force INTLC to polarity defined in

’INTLCINV’

SYCTRL

w/r

delay of CSY output (relative to PLL2)

bit[7:0]

−128..127 ± 8 µs

CSYDEL

Table 2–5: I2C control and status registers of the video backend

(Registers are set to ’0’ at reset, default values are recommendations)

I2C Sub

address

Number

of bits

Mode

Function

Default

Name

(hex)

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