VDP3133Y datasheet(34/76 Pages) MICRONAS

34 / 76 page

VDP 313xY

ADVANCE INFORMATION

Micronas

Picture Frame Generator

w v

bit[7:0]

reserved, set t o zero

bit[8]

enable picture frame generator

PFGEN

w h

picture frame color 12 bit wide,

bit[3:0]

0..15

blue amplitude

bit[7:4]

0..15

green amplitude

bit[11:8]

0..15

red amplitude

PFC

PFCB

PFCG

PFCR

w v

picture frame insertion contrast for R

(ampl. range: 0 to 255)

bit[3:0]

reserved, set to zero

bit[7:4]

0..13

R amplitude =

PFCR

× (PFRCT + 4)

14,15

invalid

PFRCT

w v

picture frame insertion contrast for G

(ampl. range: 0 to 255)

bit[3:0]

reserved, set to zero

bit[7:4]

0..13

G amplitude =

PFCG

× (PFGCT + 4)

14,15

invalid

PFGCT

w v

picture frame insertion contrast for B

(ampl. range: 0 to 255)

bit[3:0]

reserved, set to zero

bit[7:4]

0..13

B amplitude =

PFCB

× (PFBCT + 4)

14,15

invalid

PFBCT

w v

bit[8:0]

horizontal picture frame begin

code 0 = picture frame generator horizontally disabled

code 1FF = full frame

0PFGHB

w v

bit[8:0]

horizontal picture frame end

PFGHE

w v

bit[8:0]

vertical picture frame begin

code 0 = picture frame generator vertically disabled

270

PFGVB

w v

bit[8:0]

vertical picture frame end

PFGVE

Priority Decoder

w v

bit[7]

0/1

select main/side setting for

contrast,brightness,matrix

0SIDE

w v

bit[7]

0/1

disable/enable peaking transient

suppression when signal is

switched to the picture frame

PKTRNS

Table 2–5: I2C control and status registers of the video backend

(Registers are set to ’0’ at reset, default values are recommendations)

I2C Sub

address

Number

of bits

Mode

Function

Default

Name

(hex)

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