VDP3133Y datasheet(33/76 Pages) MICRONAS

33 / 76 page

ADVANCE INFORMATION

VDP 313xY

Micronas

Chrominance Channel

w/r

luma/chroma matching delay

bit[2:0]

−3...3

variable chroma delay

bit[7:3]

reserved, set to 0

LCM

CDEL

w v

digital transient improvement

bit[3:0]

0..15

coring value

bit[7:4]

0..15

DTI gain

bit[8]

0/1

narrow/wide bandwidth mode

DTI

DTICO

DTIGA

DTIMO

Inverse Matrix

w v

main matrix coefficient R

−Y=MR1M×C

B+MR2M×CR

bit[8:0]

−256/128 ... 255/128

bit[8:0]

−256/128 ... 255/128

MR1M,

MR2M

w v

main matrix coefficient G

−Y= MG1M×C

B+MG2M×CR

bit[8:0]

−256/128 ... 255/128

bit[8:0]

−256/128 ... 255/128

−22

−44

MG1M,

MG2M

w v

main matrix coefficient B

−Y=MB1M×C

B + MB2M×CR

bit[8:0]

−256/128 ... 255/128

bit[8:0]

−256/128 ... 255/128

113

MB1M,

MB2M

w v

side matrix coefficient R

−Y=MR1S×C

B + MR2S×CR

bit[8:0]

−256/128 ... 255/128

bit[8:0]

−256/128 ... 255/128

MR1S,

MR2S

w v

side matrix coefficient G

−Y= MG1S×C

B + MG2S×CR

bit[8:0]

−256/128 ... 255/128

bit[8:0]

−256/128 ... 255/128

−19

−37

MG1S,

MG2S

w v

side matrix coefficient B

−Y=MB1S×C

B + MB2S×CR

bit[8:0]

−256/128 ... 255/128

bit[8:0]

−256/128 ... 255/128

MB1S,

MB2S

Table 2–5: I2C control and status registers of the video backend

(Registers are set to ’0’ at reset, default values are recommendations)

I2C Sub

address

Number

of bits

Mode

Function

Default

Name

(hex)

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