MIC2128 datasheet(15/32 Pages) MICROCHIP

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 2016 Microchip Technology Inc.

DS20005620A-page 15

MIC2128

3.8

Internal High Voltage LDO Output

Pin (PVDD)

Internal high voltage LDO Output of the MIC2128.

PVDD is the supply for the low-side MOSFET driver and

for floating high-side MOSFET driver. Connect a

minimum of 4.7 µF low ESR ceramic capacitor from

PVDD to PGND.

3.9

EXTVDD

Supply to the internal low voltage LDO. Connect

EXTVDD to the output of the Buck converter if it is

between 4.7V to 14V to improve system efficiency.

Bypass EXTVDD with a minimum of 1 µF low ESR

ceramic capacitor.

3.10

Enable Input Pin (EN)

EN is a logic input. Connect to logic high to enable the

converter and connect to logic low to disable the

converter.

3.11

Switching Frequency

Programming Input Pin (FREQ)

Switching Frequency Programming Input. Connect to

mid-point of the resistor divider formed between VIN

and AGND to set switching frequency of the converter.

Tie FREQ to VIN to set the switching frequency to

800 kHz. Refer to Section 5.1 “Setting the Switching

Frequency”

for more details.

3.12

Soft-Start Time Setting Capacitor

Connection Pin (SS)

Soft-Start time setting capacitor connection pin.

Connect a ceramic capacitor from SS to AGND to set

the output Soft-Start time. Refer to Section 5.3

“Setting the Soft-Start Time”

section for further

details.

3.13

Feedback Input Pin (FB)

FB is input to the transconductance amplifier of the

control loop. The control loop regulates the FB voltage

to 0.6V. Connect FB node to mid-point of the resistor

divider between output and AGND.

3.14

Analog Ground Pin (AGND)

AGND is reference to the analog control circuits inside

the MIC2128. Connect AGND to PGND at one point on

PCB.

3.15

Bias Voltage Pin (VDD)

Supply for the MIC2128 internal analog circuits. Con-

nect VDD to PVDD of the MIC2128 through a low pass

filter. Connect a minimum of 4.7 µF low ESR ceramic

capacitor from VDD to AGND for decoupling.

3.16

Input Voltage Pin (VIN)

Supply Input to the internal high voltage LDO. Connect

to the main power source and bypass to PGND with a

minimum of 0.1 µF low ESR ceramic capacitor.

3.17

Exposed Pad (EP)

Connect to AGND copper plane to improve thermal

performance of the MIC2128.

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