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MCP3914 bảng dữ liệu(PDF) 60 Page - Microchip Technology |
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MCP3914 bảng dữ liệu(HTML) 60 Page - Microchip Technology |
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60 / 80 page ![]() MCP3914 DS20005216A-page 60 2013 Microchip Technology Inc. 8.3 PHASE0 Register – Phase Configuration Register for Channel Pairs 6/7 and 4/5 Any write to this register automatically resets and restarts all active ADCs. Name Bits Address Cof. PHASE0 24 0x09 R/W REGISTER 8-3: PHASE0 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASED<11> PHASED<10> PHASED<9> PHASED<8> PHASED<7> PHASED<6> PHASED<5> PHASED<4> bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASED<3> PHASED<2> PHASED<1> PHASED<0> PHASEC<11> PHASEC<10> PHASEC<9> PHASEC<8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEC<7> PHASEC<6> PHASEC<5> PHASEC<4> PHASEC<3> PHASEC<2> PHASEC<1> PHASEC<0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-12 PHASED<11:0> Phase delay between channels CH6 and CH7 (reference). Delay = PHASED<11:0> decimal code/DMCLK bit 11-0 PHASEC<11:0> Phase delay between channels CH4 and CH5 (reference). Delay = PHASEC<11:0> decimal code/DMCLK |
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