MCP3914 datasheet(24/80 Pages) MICROCHIP

24 / 80 page

MCP3914

DS20005216A-page 24

 2013 Microchip Technology Inc.

4.11

Total Harmonic Distortion (THD)

The total harmonic distortion is the ratio of the output

harmonic’s power to the fundamental signal power for

a sine wave input, and is defined in Equation 4-7.

EQUATION 4-7:

The THD calculation includes the first 35 harmonics for

the MCP3914 specifications. The THD is usually

measured only with respect to the ten first harmonics,

which leads artificially to better figures. THD is

sometimes expressed in %. Equation 4-8 converts the

THD in %.

EQUATION 4-8:

This specification depends mainly on the DITHER

setting.

4.12

Spurious-Free Dynamic Range

(SFDR)

SFDR is the ratio between the output power of the

fundamental and the highest spur in the frequency

spectrum (see Equation 4-9). The spur frequency is not

necessarily a harmonic of the fundamental, even

though it is usually the case. This figure represents the

dynamic range of the ADC when a full-scale signal is

used at the input. This specification depends mainly on

the DITHER setting.

EQUATION 4-9:

4.13

MCP3914 Delta-Sigma

Architecture

The MCP3914 incorporates eight delta-sigma ADCs

with a multi-bit architecture. A delta-sigma ADC is an

oversampling converter that incorporates a built-in

modulator, which digitizes the quantity of charges

integrated by the modulator loop (see Figure 5-1). The

quantizer is the block that is performing the

analog-to-digital conversion. The quantizer is typically

1-bit, or a simple comparator, which helps maintain the

linearity performance of the ADC (the DAC structure is,

in this case, inherently linear).

Multi-bit quantizers help to lower the quantization error

(the error fed back in the loop can be very large with

1-bit quantizers) without changing the order of the

modulator or the OSR, which leads to better SNR

figures.

The quantizer present in each ADC channel in the

MCP3914 is a Flash ADC composed of four

comparators arranged with equally spaced thresholds

and a thermometer coding. The MCP3914 also

includes proprietary 5-level DAC architecture that is

inherently linear for improved THD figures.

4.14

Idle Tones

A delta-sigma converter is an integrating converter. It

also has a finite quantization step (least significant bit

or LSB) which can be detected by its quantizer. A DC

input voltage that is below the quantization step should

only provide an all zeros result, since the input is not

large enough to be detected. As an integrating device,

any delta-sigma ADC will show idle tones. This means

that the output will have spurs in the frequency content

that depend on the ratio between quantization step

voltage and the input voltage. These spurs are the

result of the integrated sub-quantization step inputs

that will eventually cross the quantization steps after a

long enough integration. This will induce an AC

frequency at the output of the ADC, and can be shown

in the ADC output spectrum.

These idle tones are residues that are inherent to the

quantization process and the fact that the converter is

integrating at all times without being reset. They are

residues of the finite resolution of the conversion

process. They are very difficult to attenuate and they

are heavily signal dependent. They can degrade the

SFDR and THD of the converter, even for DC inputs.

They can be localized in the baseband of the converter

and are thus difficult to filter from the actual input signal.

For power metering applications, idle tones can be very

disturbing, because energy can be detected even at

the 50 or 60 Hz frequency, depending on the DC offset

of the ADCs, while no power is really present at the

inputs. The only practical way to suppress or attenuate

the idle tones phenomenon is to apply dithering to the

ADC. The amplitudes of the idle tones are a function of

the order of the modulator, the OSR and the number of

levels in the quantizer of the modulator. A higher order,

a higher OSR or a higher number of levels for the

quantizer will attenuate the amplitudes of the idle

tones.

4.15

Dithering

In order to suppress or attenuate the idle tones present

in any delta-sigma ADCs, dithering can be applied to

the ADC. Dithering is the process of adding an error to

the ADC feedback loop in order to “decorrelate” the

outputs and “break” the idle tone’s behavior. Usually a

random or pseudo-random generator adds an analog

THD dB



HarmonicsPower

FundamentalPower

-----------------------------------------------------





log

THD %



100

THD dB



------------------------



SFDR dB



FundamentalPower

HighestSpurPower

-----------------------------------------------------





log

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