MCP3910 datasheet(42/86 Pages) MICROCHIP

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MCP3910

DS20005116B-page 42

 2012-2014 Microchip Technology Inc.

5.13.1

DIGITAL OFFSET ERROR

CALIBRATION

The OFFCAL_CHn registers are 23-bit plus two’s

complement registers, and whose LSB value is the

same as the Channel ADC Data. These two registers

are then added bit by bit to the ADC output codes, if

EN_OFFCAL bit is enabled. Enabling the EN_OFFCAL

bit does not create a pipeline delay; the offset addition

is instantaneous. For low OSR values, only the

significant digits are added to the output (up to the

resolution of the ADC; for example, at OSR = 32, only

the 17 first bits are added).

The offset is not added when the corresponding

channel is in Reset or Shutdown mode. The

corresponding input voltage offset value added by each

LSB in these 24-bit registers is:

EQUATION 5-9:

This registers are a “Don't Care” if EN_OFFCAL = 0

(offset calibration disabled), but their value is not

cleared by the EN_OFFCAL bit.

5.13.2

DIGITAL GAIN ERROR

CALIBRATION

This register is a 24-bit signed MSB first coding with a

range of -1x to +0.9999999x (from 0x80000 to

0x7FFFFF). The gain calibration adds 1x to this

channel bit by bit, after offset calibration. The range of

the gain calibration is thus from 0x to 1.9999999x (from

0x80000 to 0x7FFFFF). The LSB corresponds to a 2-23

increment in the multiplier.

Enabling EN_GAINCAL creates a pipeline delay of

24 DMCLK periods on all channels. All data ready

pulses are delayed by 24 DMCLK periods, starting

from data ready following the command enabling

EN_GAINCAL bit. The gain calibration is effective on

the next data ready following the command enabling

EN_GAINCAL bit.

The digital gain calibration does not function when the

corresponding channel is in Reset or Shutdown mode.

The gain multiplier value for an LSB in these 24-bit

registers is:

EQUATION 5-10:

This register is a “Don't Care” if EN_GAINCAL = 0

(offset calibration disabled), but its value is not cleared

by the EN_GAINCAL bit.

The output data on each channel is kept to either 7FFF

or 8000 (16-bit mode) or 7FFFFF or 800000 (24-bit

mode) if the output results are out of bounds after all

calibrations are performed.

OFFSET(1LSB) = VREF/(PGA_CHn x 1.5 x 8388608)

GAIN (1LSB) = 1/8388608

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