MCP3910 datasheet(38/86 Pages) MICROCHIP

38 / 86 page

MCP3910

DS20005116B-page 38

 2012-2014 Microchip Technology Inc.

FIGURE 5-7:

VREF Tempco vs. VREFCAL

Trim Code Chart.

5.6.4

VOLTAGE REFERENCE BUFFERS

Each channel includes a voltage reference buffer tied

to the REFIN+/OUT pin, which allows the device to

properly charge the internal capacitors with the voltage

reference signals, even in the case of an external

voltage reference connection with weak load regulation

specifications. This ensures that the correct amount of

current is sourced to each channel to guarantee their

accuracy specifications, and diminishes the constraints

on the voltage reference load regulation.

5.7

Power-On Reset

The MCP3910 contains an internal POR circuit that

monitors both analog and digital supply voltages during

operation. The typical threshold for a power-up event

detection is 2.0V ±5% and a typical start-up time (tPOR)

of 50 µs. The POR circuit has a built-in hysteresis for

improved transient spike immunity that has a typical

value of 200 mV. Proper decoupling capacitors (0.1 µF

ceramic and 10 µF) should be mounted as close as

possible to the AVDD and DVDD pins, providing addi-

tional transient immunity.

Figure 5-8 illustrates the different conditions at a

power-up and a power-down event under typical

conditions. All internal DC biases are settled at least

1 ms after system POR, under worst-case conditions.

Any data ready pulse occurring within 1 ms plus the

sinc filter settling time after system reset should be

ignored to ensure proper accuracy. After POR, data

ready pulses are present at the pin with all the default

conditions in the configuration registers.

Both AVDD and DVDD are monitored, so either power

supply can sequence first.

FIGURE 5-8:

Power-On Reset Operation.

128

192

256

VREFCAL Register Trim Code (decimal)

POR

State

Power-Up

Normal

POR

State

Biases are

unsettled.

Conversions

started here may

not be accurate.

Biases are settled.

Conversions started

here are accurate.

Analog biases

settling time

SINC filter

settling

time

Voltage

(AVDD, DVDD)

Time

POR Threshold

up (2.0V typical)

(1.8V typical)

tPOR

Operation

Any

data

read

pulse

occurring during this time

can yield inaccurate output

data. It is recommended to

discard them.

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