PCM4202DBR datasheet(17/26 Pages) BURR-BROWN

17 / 26 page

PCM4202

SBAS290B − JULY 2003 − SEPTEMBER 2004

www.ti.com

DSD OUTPUT MODE OPERATION

The output port DSD mode operation consists of a single

DSD data clock signal, DSDBCK (pin 17), along with two

synchronous DSD data lines, DSDR (pin 15) and DSDL

(pin 16). The data lines correspond to Right and Left

channels, respectively. The DSD output rate is determined

by the sampling mode settings for the device, discussed

in the Sampling Modes section of this datasheet.

For DSD output data, the serial port is configured in Master

mode, with the DSDBCK derived from the system clock

input,

SCKI.

The

DSDBCK

equivalent

to the

oversampling

clock

supplied

the

delta-sigma

modulators. The DSD data outputs, DSDR through DSDL,

are synchronous to the DSDBCK. The clock and data lines

are then connected to a data capture or processing device.

Figure 7 illustrates the DSD port timing for both the DSD

output mode.

HIGH-PASS FILTER

A digital high-pass filter is available for removing the DC

component of the digitized input signal. The filter is located

at the output of the digital decimation filter, and is available

only when using PCM output data formats. The high-pass

filter can be enabled or disabled for both the Left and Right

channels using the HPFD input (pin 12). Driving the HPFD

input low enables the high-pass filter. Driving the HPFD

input high disables the high-pass filter.

The −3dB corner frequency for the high-pass filter scales

with the output sampling rate, where f−3dB = fS/48000,

where fS is the output sampling rate.

CLIPPING FLAGS

The PCM4202 includes a clipping flag output for each

channel. The outputs are designated CLIPL (pin 21) and

CLIPR (pin 20), corresponding to the Left and Right

channels, respectively. The clipping flags are only

available when using PCM output data formats.

A clipping flag is forced high as soon as the digital output

of the decimation filter exceeds the full-scale range for the

corresponding channel. The clipping flag output is held

high for a maximum of (256 x N) / fS seconds, where N =

128 for Single Rate sampling mode, 256 for Dual Rate

sampling mode, and 512 for Quad Rate sampling mode.

If the decimation filter output does not exceed the full-scale

range during the initial hold period, the output returns to a

low state upon termination of the hold period.

DSDBCK

DSDL

DSDR

DCKHL

DCKP

P ARAM E T E R

DE S CRIP T IO N

M IN

M A X

UNITS

156

DCKDO

LRCK pulse width

DCKP

LRCK active edge to BCK sampling edge delay

Data setup time

Figure 7. DSD Data Port Timing

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