TMS320VC5407 datasheet(33/110 Pages) TI

33 / 110 page

Functional Overview

November 2001 − Revised April 2004

SPRS007D

The 5407/5404 has an internal register that holds the MSB of the last address used for a read or write operation

in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of the address

used for the current read does not match that contained in this internal register, the MSTRB (memory strobe)

signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new

address. The contents of the internal register are replaced with the MSB for the read of the current address.

If the MSB of the address used for the current read matches the bits in the register, a normal read cycle occurs.

In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory

bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts

are avoided by inserting an extra cycle. For more information, see Section 3.11 of this document.

The bank-switching mechanism automatically inserts one extra cycle in the following cases:

•

A memory read followed by another memory read from a different memory bank.

•

A program-memory read followed by a data-memory read.

•

A data-memory read followed by a program-memory read.

•

A program-memory read followed by another program-memory read from a different page.

3.6.3 Bus Holders

The 5407/5404 has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers

of the address bus (A[17−0]), data bus (D[15−0]), and the HPI data bus (HD[7−0]). Bus keeper

enabling/disabling is described in Table 3−5.

Table 3−6. Bus Holder Control Bits

HPI16 PIN

HBH

D[15−0]

A[17−0]

HD[7−0]

OFF

3.7

Parallel I/O Ports

The 5407/5404 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the

PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The 5407/5404 can

interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding

circuits.

3.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16)

The 5407/5404 host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard

8-bit HPI found on earlier TMS320C54x DSPs (542, 545, 548, and 549). The 5407/5404 HPI can be used

to interface to an 8-bit or 16-bit host. When the address and data buses for external I/O is not used (to interface

to external devices in program/data/IO spaces), the 5407/5404 HPI can be configured as an HPI16 to interface

to a 16-bit host. This configuration can be accomplished by connecting the HPI16 pin to logic “1”.

TMS320VC5407 bảng dữ liệu(PDF) 33 Page - Texas Instruments

TMS320VC5407 bảng dữ liệu(HTML) 33 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL