17

ST16C552/552A

Rev. 3.40

A2 A1 A0

Register

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

[Default]

Note 5*

Printer Port Register Set: Note 3*

[X]

0

0

PR[00]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-0

[X]

0

0

PR[00]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-0

[X]

0

1

SR[4F]

-Busy

-ACK

PE

SLCT

Error

-IRQ

logic

logic

State

“1”

“1”

[X]

0

1

IOSEL

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-0

[X]

1

0

COM[E0]

logic

logic

logic

-INTP

-SLCTIN

INIT

-Auto

-STROBE

“1”

“1”

“1”

Enable

FDXT

[X]

1

0

CON[00]

[X]

[X]

PD 0-7

-INTP

-SLCTIN

INIT

-Auto

-STROBE

IN/OUT

Enable

FDXT

Note 1* The General Register set is accessible only when CS A or CS B is a logic 0.

Note 2* The Baud Rate register set is accessible only when CS A or CS B is a logic 0 and LCR bit-7 is a logic 1.

Note 3*: Printer Port Register set is accessible only when -CSP is a logic 0 in conjunction with the states of the

interface signal BIDEN and Printer Control Register bit-5 or IOSEL register.

Note 5* The value between the square brackets represents the register’s initialized HEX value, X =N/A.

MODEM (UART) REGISTER DESCRIPTIONS

Transmit (THR) and Receive (RHR) Holding Reg-

isters

The serial transmitter section consists of an 8-bit

Transmit Hold Register (THR) and Transmit Shift

Register (TSR). The status of the THR is provided in

the Line Status Register (LSR). Writing to the THR

transfers the contents of the data bus (D7-D0) to the

THR, providing that the THR or TSR is empty. The

THR empty flag in the LSR register will be set to a logic

1 when the transmitter is empty or when data is

transferred to the TSR. Note that a write operation can

be performed when the transmit holding register

empty flag is set (logic 0 = FIFO full, logic 1= at least

one FIFO location available).

The serial receive section also contains an 8-bit

Receive Holding Register, RHR. Receive data is

removed from the 552/552A and receive FIFO by

reading the RHR register. The receive section pro-

vides a mechanism to prevent false starts. On the

falling edge of a start or false start bit, an internal

receiver counter starts counting clocks at the 16x

clock rate. After 7 1/2 clocks the start bit time should

be shifted to the center of the start bit. At this time the

start bit is sampled and if it is still a logic 0 it is

validated. Evaluating the start bit in this manner

prevents the receiver from assembling a false charac-

ter. Receiver status codes will be posted in the LSR.