TVP7002IPZP datasheet(24/58 Pages) TI1

tên linh kiện	TVP7002IPZP

Giải thích chi tiết về linh kiện	TRIPLE 8-/10-BIT 165-/110-MSPS VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL

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Power

Reset

I C

5 ms

1 µs

TVP7002

SLES206C – MAY 2007 – REVISED APRIL 2013

www.ti.com

Power Up, Reset, and Initialization

No specific power-up sequence is required, but all power supplies should be active and stable within 500 ms of

each other. RESETB may be low during power up, but must remain low for at least 1

μs after the power supplies

become stable. Alternatively, reset may be asserted any time with minimum 5-ms delay after power-up and must

remain asserted for at least 1

μs. Reset timing is shown in Figure 7. I2C SCL and SDA signals must not change

state until the TVP7002 reset sequence has been completed. Keeping RESETB low prior to any I2C activity will

prevent this. Table 11 shows the status of the TVP7002 terminals during and immediately after reset.

Table 11. Output Mode Per Reset Sequence State

OUTPUT MODE

SIGNAL NAME

DURING RESET

RESET COMPLETED

Default condition

R[9:0], B[9:0], G[9:0]

High impedance

(see bit 0 of subaddress 17h)

Default condition

HSOUT, VSOUT, FIDOUT, DATACLK

High impedance

(see bit 0 of subaddress 17h)

Default condition

SOGOUT

High impedance

(see bit 1 of subaddress 17h)

Figure 7. Reset Timing

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TVP7002IPZP bảng dữ liệu(PDF) 24 Page - Texas Instruments