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TUSB9261IPAPRQ1 bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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TUSB9261IPAPRQ1 bảng dữ liệu(HTML) 8 Page - Texas Instruments |
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8 / 24 page ![]() TUSB9261-Q1 SLLSEE2A – JANUARY 2014 – REVISED JANUARY 2014 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE UNIT VDD Steady-state supply voltage –0.3 to 1.4 V VDD33/ Steady-state supply voltage –0.3 to 3.8 V VDDA33 USB 2.0 DP/DM –0.3 to 3.8 SuperSpeed USB TXP/M and RXP/M –0.3 to 3.8 VIO SATA TXP/M and RXP/M –0.3 to 3.8 V XI/XO –0.3 to 1.98 3.3V Tolerant I/O –0.3 to 3.8 VUSB_VBUS Voltage at USB_VBUS pad –0.3 to 1.2 V TSTG Storage temperature range -65 to 150 °C TJ Operating junction temperature range -40 t o 105 °C Human-body model (HBM) AEC-Q100 Classification Level H2 2 kV Corner pins 750 ESD rating AEQ-Q100 Classification Level C4B Charged-device model Non-corner pins 500 V (CDM) except USB_R1 AEQ-Q100 Classification Level C3 USB_R1 450 THERMAL INFORMATION TUSB9261-Q1 THERMAL METRIC(1) PAP UNITS 64 PINS θJA Junction-to-ambient thermal resistance(2) 30.2 θJCtop Junction-to-case (top) thermal resistance(3) 11 θJB Junction-to-board thermal resistance(4) 6.1 °C/W ψJT Junction-to-top characterization parameter(5) .04 ψJB Junction-to-board characterization parameter(6) 6.1 θJCbot Junction-to-case (bottom) thermal resistance(7) 0.9 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Digital 1.1 supply voltage 1.045 1.1 1.155 V VDD33 Digital 3.3 supply voltage 3 3.3 3.6 V VDDA33 Analog 3.3 supply voltage 3 3.3 3.6 V 8 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links :TUSB9261-Q1 |
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