TUSB9261-Q1

SLLSEE2A – JANUARY 2014 – REVISED JANUARY 2014

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Table 6. JTAG, GPIO, and PWM Signals

TERMINAL

I/O

DESCRIPTION

PIN

NAME

NO.

I

JTAG_TCK

25

JTAG test clock

PD

I

JTAG_TDI

26

JTAG test data in

PU

O

JTAG_TDO

27

JTAG test data out

PD

I

JTAG_TMS

28

JTAG test mode select

PU

I

JTAG_TRSTz

29

JTAG test reset

PD

I/O

GPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a

GPIO9/UART_TX

6

PU

UART channel. SeeTable 8 for firmware configuration defaults.

I/O

GPIO/UART receiver. This terminal can be configured as a GPIO or as the receiver for a UART

GPIO8/UART_RX

5

PU

channel. SeeTable 8 for firmware configuration defaults.

I/O

GPIO7

16

PD

I/O

GPIO6

15

PD

I/O

GPIO5

14

PD

I/O

GPIO4

13

PD

Configurable as general purpose input/outputs. SeeTable 8 for firmware configuration defaults.

I/O

GPIO3

11

PD

I/O

GPIO2

10

PD

I/O

GPIO1

9

PD

I/O

GPIO0

8

PD

O

PWM0

2

Pulse Width Modulation (PWM) which can be used to drive status LED's. SeeTable 8 for firmware

configuration defaults.

O

PWM1

3

(1)

PWM pull down resistors are disabled by default. A firmware modification is required to turn them on. All other internal pull up/down

resistors are enabled by default.

6

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