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TUSB8020BPHPR bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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TUSB8020BPHPR bảng dữ liệu(HTML) 8 Page - Texas Instruments |
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8 / 43 page ![]() Thd_io Tsu_io Td1 Td2 GRSTz VDD33 VDD MISC_IO TUSB8020B SLLSEF6A – JULY 2014 – REVISED JULY 2014 www.ti.com 7.5 3.3-V I/O Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER OPERATION TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage(1) VDD33 2 VDD33 V VIL Low-level input voltage(1) VDD33 0 0.8 V VI Input voltage 0 VDD33 V VO Output voltage(2) 0 VDD33 V tt Input transition time (trise and tfall) 0 25 ns 0.13 × Vhys Input hysteresis(3) V VDD33 VOH High-level output voltage VDD33 IOH = –4 mA 2.4 V VOL Low-level output voltage VDD33 IOL = 4 mA 0.4 V IOZ High-impedance, output current(2) VDD33 VI = 0 to VDD33 ±20 µA High-impedance, output current with IOZP VDD33 VI = 0 to VDD33 ±225 µA internal pullup or pulldown resistor(4) II Input current(5) VDD33 VI = 0 to VDD33 ±15 µA (1) Applies to external inputs and bidirectional buffers (2) Applies to external outputs and bidirectional buffers (3) Applies to GRSTz (4) Applies to pins with internal pullups/pulldowns (5) Applies to external input buffers 7.6 Power-Up Timing Requirements MIN TYP MAX UNIT td1 VDD33 stable before VDD stable. No timing relationship between VDD33 and VDD 0 ms td2 VDD and VDD33 stable before deassertion of GRSTZ. 3 ms tsu_io Setup for MISC inputs sampled at the deassertion of GRSTZ(1) 0.1 µs thd_io Hold for MISC inputs sampled at the deassertion of GRSTZ. (1) 0.1 µs tVDD33_RAMP VDD33 supply ramp requirements 0.2 100 ms tVDD_RAMP VDD supply ramp requirements 0.2 100 ms (1) Miscellaneous pins sampled at deassertion of GRSTZ: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN1, and BATEN2 Figure 1. Power-Up Timing Requirements 8 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: TUSB8020B |
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