CAP1114 datasheet(18/102 Pages) MICROCHIP

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Multiple Channel Capacitive Touch Sensor and LED Driver

Datasheet

Revision 1.1 (02-04-11)

SMSC CAP1114

DATASHEET

Chapter 4 Communications

The CAP1114 communicates via the SMBus or I2C communications protocols.

APPLICATION NOTE: Upon power up, the CAP1114 will not respond to any SMBus communications for 10ms. After

this time, full functionality is available.

4.1

System Management Bus Protocol

The CAP1114 communicates with a host controller, such as an SMSC SIO, through the SMBus. The

SMBus is a two-wire serial communication protocol between a computer host and its peripheral

devices. A detailed timing diagram is shown in Figure 4.1. Stretching of the SMCLK signal is supported;

however, the CAP1114 will not stretch the clock signal.

4.1.1

SMBus Start Bit

The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic

‘0’ state while the SMBus Clock line is in a logic ‘1’ state.

4.1.2

SMBus Address and RD / WR Bit

The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If

this RD / WR bit is a logic ‘0’, the SMBus Host is writing data to the client device. If this RD / WR bit

is a logic ‘1’, the SMBus Host is reading data from the client device.

The CAP1114 responds to the slave address 0101_000xb. Multiple addressing options are available.

For more information contact SMSC.

4.1.3

SMBus Data Bytes

All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.

4.1.4

SMBus ACK and NACK Bits

The SMBus client will acknowledge all data bytes that it receives. This is done by the client device

pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. This applies to both

the Write Byte and Block Write protocols.

Figure 4.1 SMBus Timing Diagram

SMDATA

SMCLK

BUF

S - Start Condition

P - Stop Condition

T HIGH

T LOW

T HD:STA

T SU:STO

T HD:STA

T HD:DAT

T SU:DAT

T SU:STA

T FALL

T RISE

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