GXM datasheet(172/244 Pages) NSC

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Revision 3.1

Virtual Subsystem Architecture (Continued)

5.2.5

Virtual VGA Register Descriptions

This section describes the registers contained in the

graphics pipeline used for VGA emulation. The graphics

pipeline

maps

200h

locations

starting

GX_BASE+8100h. Refer to Section 4.1.2 “Control Regis-

ters” on page 94 for instructions on accessing these regis-

ters.

The registers are summarized in Table 5-4, followed by

detailed bit formats in Table 5-5 on page 173.

Table 5-4. Virtual VGA Register Summary

GX_BASE+

Memory Offset

Type

Function

Default Value

8210h-8213h

R/W

GP_VGA_BASE VGA

Graphics Pipeline VGA Memory Base Address Register — Specifies the offset

of the VGA memory, starting from the base of graphics memory.

xxxxxxxxh

8214h-8217h

R/W

GP_VGA_LATCH

Graphics Pipeline VGA Display Latch Register — Provides a memory mapped

way to read or write the VGA display latch.

xxxxxxxxh

8140h-8143h

R/W

GP_VGA_WRITE

Graphics Pipeline VGA Write Patch Control Register — Controls the VGA mem-

ory write path in the graphics pipeline.

xxxxxxxxh

8144h-8147h

R/W

GP_VGA_READ

Graphics Pipeline VGA Read Patch Control Register — Controls the VGA mem-

ory read path in the graphics pipeline.

00000000h

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