GXM datasheet(118/244 Pages) NSC

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118

Revision 3.1

Integrated Functions (Continued)

4.3.7

SDRAM Interface Clocking

The GXm processor drives the SDCLK to the SDRAMs;

one for each DIMM bank. All the control, data, and

address signals driven by the memory controller are sam-

pled by the SDRAM at the rising edge of SDCLK. SDCLK-

OUT is a reference signal used to generate SDCLKIN.

Read data is sampled by the memory controller at the ris-

ing edge of SDCLKIN.

The delay for SDCLKIN must be designed so that it lags

the SDCLKs at the DRAM by approximately 2ns. The

delay should also include the SDCLK transmission line

delay. The SDCLK traces on the board need to be laid out

so there is no skew between each of the four sinks. These

guidelines allow the memory interface to be closer to the

DRAM specifications. They improve performance by run-

ning the SDCLK up to frequencies of 100 MHz and a CAS

latency of two.

Figure 4-9. SDCLKIN Clocking

DIMM

SDCLK[3:0]

Delay

SDCLKOUT

SDCLKIN

SDCLK0

SDCLK1

SDCLK2

SDCLK3

Geode™ GXm

Processor

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